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gigeresk wants to merge 18 commits into from
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SC Schema Upgrade #178

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b7a4fc4
Update examples to new SC, add two devices locally.
gigeresk Sep 24, 2025
24c0217
Update to match recent SC changes
gigeresk Sep 30, 2025
4f032e8
Remove pcf from adder example
gigeresk Sep 30, 2025
60f6ee1
Remove comments
gigeresk Sep 30, 2025
b4bc55e
SC main CI
gigeresk Sep 30, 2025
7619faa
Fix eth_mac_1g and add LogikDevice class
gigeresk Oct 1, 2025
0d85446
remove convert_bitstream step
gigeresk Oct 2, 2025
1822dc7
recommit convert_bitstream, etc
gigeresk Oct 3, 2025
5f0dc6d
add init.py to devices/
gigeresk Oct 3, 2025
fcad457
Remove K4_N8_6x6
gigeresk Oct 3, 2025
4de48c6
Remove dvice files
gigeresk Oct 3, 2025
0ec62fa
flake8
gigeresk Oct 3, 2025
e283fc4
Lock workflow to head of sc main
gigeresk Oct 3, 2025
ff3d9a6
Fix CI tests
gigeresk Oct 3, 2025
35a0b5b
placate flake8
gigeresk Oct 3, 2025
0d24943
trying to make CI pass
gigeresk Oct 3, 2025
0e39ba6
please pass CI
gigeresk Oct 3, 2025
e026084
Set builddir local
gigeresk Oct 3, 2025
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please pass CI
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@gigeresk
gigeresk committed Oct 3, 2025
commit 0e39ba64ea0665851c709e52fb8a133831d26874
2 changes: 1 addition & 1 deletion tests/examples/test_files.py
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Expand Up @@ -6,7 +6,7 @@
from logik.demo.z1000 import z1000


def test_file_paths(part):
def test_file_paths():
project = siliconcompiler.FPGA("test")
project.set_fpga(z1000())

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