Multi-platform nightly builds of open source digital design and verification tools

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

Quick-to-create and easy-to-use platform for experimentation with Linux on the open-source SystemC RISC-V based virtual prototype GUI-VP

RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute for Complex Systems, Johannes Kepler University, Linz.

【CVPR 2025 Highlight】MonSter: Marry Monodepth to Stereo Unleashes Power

Code for paper "Boosting Continual Learning of Vision-Language Models via Mixture-of-Experts Adapters" CVPR2024

Functional verification project for the CORE-V family of RISC-V cores.

[ICCV' 2025] The official implementation for Bilinear Prompt Tuning.

Official implementation of "Mixture of Experts Meets Prompt-Based Continual Learning" (NeurIPS 2024)

This repo hold information on the open-standard OVP APIs

A FPGA friendly 32 bit RISC-V CPU implementation

[CVPR 2025] DEFOM-Stereo: Depth foundation model based stereo matching

Symbolic Execution of SystemC TLM Peripherals

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

A modeling library with virtual components for SystemC and TLM simulators

This tool translates synthesizable SystemC code to synthesizable SystemVerilog.

The PicoNut project at the Technical University of Applied Sciences Augsburg aims to develop a minimal and at the same time flexibly expandable RISC-V processor that works on common FPGA hardware a…

An ARMv8 virtual platform based on QEMU and VCML

Scripts to build avp64 target software

An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM

DeepEP: an efficient expert-parallel communication library

s1: Simple test-time scaling

DeepSeek-VL2: Mixture-of-Experts Vision-Language Models for Advanced Multimodal Understanding