TEA: Time-Proportional Event Analysis

• ISCA 2023 Slides: ISCA_2023_TEA_Time-Proportional_Event_Analysis.pdf

Please follow the official chipyard/firesim documentation for setting up this repository.

The paper used the DDR3FRFCFS_FireSimIPAUltraBoom2MBL2PrftRoCCConfig-BaseF1Config1Mem configuration running on the Alveo U250. You can use the firesim manager to run your simulations or do it manually. To trigger the collection of data and running the profilers the command line that firesim executes must be extended to instantiate the respective TraceDoctor workers. This is an example (newlines and comments added for explanation and must be removed to execute the firesim driver):

./FireSim-u250 +permissive [default firesim parameters]
+tracedoctor-buffers=128,256 # Adjust according to your host resources
+tracedoctor-worker=oracle,file:oracle.csv.gz # Oracle Data
+tracedoctor-worker=tea_gold,file:tea_severity_hist.csv.gz,file:tea_cycle_hist.csv.gz # TEA Golden Model
+tracedoctor-worker=tea_sampler,samplingPeriod:800000,file:tea_sampler_4khz.csv.gz # TEA Profiler at 4 kHz
[more default firesim parameter]

Oracle produces statistics per instruction address in one CSV. TEA produces histograms in which each address and each event combination does have the distribution of stall cycles (severity, first file) and a distribution of total cycles (stall + commit cycles, second file). These histograms are done in a compressed notation (bucket:count/bucket:count/...). The event combinations is a bit field for which each bit represents one event that the instruction experienced. For more details which bits are which event have a look at tracedoctor_tea.h. The 2 histogramms (be carefull to substract the severity off the total cycles to not double account for cycles) combined will create the golden PICS the instructions. The TEA sampler outputs all samples into one file which must be processed and aggregated to generate the PICS.

Scripts from https://github.com/EECS-NTNU/pperf, https://github.com/bgottschall/pythonTools and https://github.com/bgottschall/plotgen might help you in parsing and processing the data.

Chipyard Framework

Quick Links

• Stable Documentation: https://chipyard.readthedocs.io/
• User Question Forum: https://groups.google.com/forum/#!forum/chipyard
• Bugs and Feature Requests: https://github.com/ucb-bar/chipyard/issues

Using Chipyard

To get started using Chipyard, see the stable documentation on the Chipyard documentation site: https://chipyard.readthedocs.io/

What is Chipyard

Chipyard is an open source framework for agile development of Chisel-based systems-on-chip. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other Berkeley projects to produce a RISC-V SoC with everything from MMIO-mapped peripherals to custom accelerators. Chipyard contains processor cores (Rocket, BOOM, CVA6 (Ariane)), accelerators (Hwacha, Gemmini, NVDLA), memory systems, and additional peripherals and tooling to help create a full featured SoC. Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation (FireSim), automated VLSI flows (Hammer), and software workload generation for bare-metal and Linux-based systems (FireMarshal). Chipyard is actively developed in the Berkeley Architecture Research Group in the Electrical Engineering and Computer Sciences Department at the University of California, Berkeley.

Resources

• Chipyard Stable Documentation: https://chipyard.readthedocs.io/
• Chipyard (x FireSim) Tutorial: https://fires.im/tutorial
• Chipyard Basics slides: https://fires.im/isca22-slides-pdf/02_chipyard_basics.pdf
• Chipyard Tutorial Exercise slides: https://fires.im/isca22-slides-pdf/03_building_custom_socs.pdf

Need help?

• Join the Chipyard Mailing List: https://groups.google.com/forum/#!forum/chipyard
• If you find a bug or would like propose a feature, post an issue on this repo: https://github.com/ucb-bar/chipyard/issues

Contributing

• See CONTRIBUTING.md

Attribution and Chipyard-related Publications

If used for research, please cite Chipyard by the following publication:

@article{chipyard,
  author={Amid, Alon and Biancolin, David and Gonzalez, Abraham and Grubb, Daniel and Karandikar, Sagar and Liew, Harrison and Magyar,   Albert and Mao, Howard and Ou, Albert and Pemberton, Nathan and Rigge, Paul and Schmidt, Colin and Wright, John and Zhao, Jerry and Shao, Yakun Sophia and Asanovi\'{c}, Krste and Nikoli\'{c}, Borivoje},
  journal={IEEE Micro},
  title={Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs},
  year={2020},
  volume={40},
  number={4},
  pages={10-21},
  doi={10.1109/MM.2020.2996616},
  ISSN={1937-4143},
}

• Chipyard
  • A. Amid, et al. IEEE Micro'20 PDF.
  • A. Amid, et al. DAC'20 PDF.
  • A. Amid, et al. ISCAS'21 PDF.

These additional publications cover many of the internal components used in Chipyard. However, for the most up-to-date details, users should refer to the Chipyard docs.

• Generators
  • Rocket Chip: K. Asanovic, et al., UCB EECS TR. PDF.
  • BOOM: C. Celio, et al., Hot Chips 30. PDF.
    • SonicBOOM (BOOMv3): J. Zhao, et al., CARRV'20. PDF.
    • COBRA (BOOM Branch Prediction): J. Zhao, et al., ISPASS'21. PDF.
  • Hwacha: Y. Lee, et al., ESSCIRC'14. PDF.
  • Gemmini: H. Genc, et al., DAC'21. PDF.
• Sims
  • FireSim: S. Karandikar, et al., ISCA'18. PDF.
    • FireSim Micro Top Picks: S. Karandikar, et al., IEEE Micro, Top Picks 2018. PDF.
    • FASED: D. Biancolin, et al., FPGA'19. PDF.
    • Golden Gate: A. Magyar, et al., ICCAD'19. PDF.
    • FirePerf: S. Karandikar, et al., ASPLOS'20. PDF.
• Tools
  • Chisel: J. Bachrach, et al., DAC'12. PDF.
  • FIRRTL: A. Izraelevitz, et al., ICCAD'17. PDF.
  • Chisel DSP: A. Wang, et al., DAC'18. PDF.
  • FireMarshal: N. Pemberton, et al., ISPASS'21. PDF.
• VLSI
  • Hammer: E. Wang, et al., ISQED'20. PDF.

Acknowledgements

This work is supported by the NSF CCRI ENS Chipyard Award #201662.