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hx30: restore RW firmware access #35

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7f78c55
lfw: restore RW firmware access by using the right pin mux
DHowett Jun 27, 2022
4ed2983
Remember whether we cut power to ourselves, and re-check during boot
DHowett Jul 30, 2022
c187ce1
Make sure we fire SHUTDOWN_COMPLETE hooks when the AP goes down
DHowett Jul 30, 2022
e6e1190
mchp/lfw: make sure we keep the EC on for long operations
DHowett Jan 23, 2023
1dd37b6
Merge remote-tracking branch 'dhowett/dh/feature/rorw' into topic/hx3…
Emantor Oct 10, 2023
bafb539
hx30: lfw: restore RW access via PINMUX
Emantor Oct 5, 2023
b782b32
hx30: power_sequence: fire SHUTDOWN_COMPLETE
Emantor Oct 5, 2023
01c1512
hx30: board: remember whether we cut power
Emantor Oct 5, 2023
5d8b6f1
mchp: lfw: stop wdt before firmware load
Emantor Oct 6, 2023
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lfw: restore RW firmware access by using the right pin mux 
The alternate function table for LFW on the hx20 contained a few
incorrect values that resulted in LFW being unable to read from flash,
which disabled the use of the RW (and in some cases the RO) firmware
image.

1. SHD_IO0 is function 1 on the MEC152x, not function 2.
2. SHD_IO2 and SHD_IO3 were not included in the alternate function table.

The alternate function table from hx20/gpio.inc is correct, but it is
missing the SPI alternate for SHD_GLK/GPIO_0056.

In the future, we may want to move to model where hx20/gpio.inc includes
hx20/lfw/gpio.inc and common pin configurations are shared.
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@DHowett
DHowett committed Jan 23, 2023
commit 7f78c555647699d82826dae434f099a78d673d8a
12 changes: 7 additions & 5 deletions board/hx20/lfw/gpio.inc
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Expand Up @@ -31,13 +31,15 @@ ALTERNATE(PIN_MASK(2, 0x30), 1, MODULE_UART, 0)
* MEC1701H SHD SPI is connected to QMSPI controller.
* QMSPI drives chip select. SHD_CS0#(GPIO_0055) must be set
* to alternate function 2 and GPIO_ODR_HIGH.
* GPIO_0055 Function 2, Bank 1 bit[13]
*/
/* GPIO_0055 Function 2, Bank 1 bit[13] */
ALTERNATE(PIN_MASK(1, 0x2000), 2, MODULE_SPI_FLASH, GPIO_ODR_HIGH)
/* SHD_CLK - GPIO_0056 Function 2, Bank 1 bit[14] */
ALTERNATE(PIN_MASK(1, 0x4000), 2, MODULE_SPI_FLASH, 0)
/* MOSI(SHD_IO0) - GPIO_0223 Function 2, Bank 4 bit[19] */
/* MOSI(SHD_IO0) - GPIO_0223 Function 1, Bank 4 bit[19] */
/* MISO(SHD_IO1) - GPIO_0224 Function 2, Bank 4 bit[20] */
ALTERNATE(PIN_MASK(4, 0x180000), 2, MODULE_SPI_FLASH, 0)


/* nWP(SHD_IO2) - GPIO_0227 Function 1, Bank 4 bit[23] */
ALTERNATE(PIN_MASK(4, 0x880000), 1, MODULE_SPI_FLASH, 0)
ALTERNATE(PIN_MASK(4, 0x100000), 2, MODULE_SPI_FLASH, 0)
/* nHOLD(SHD_IO3) - GPIO_0016 Function 2, Bank 0 bit[14] */
ALTERNATE(PIN_MASK(0, 0x4000), 2, MODULE_SPI_FLASH, 0)