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  • remove redundant assign code
  • adjust some MUXDEF to IFDEF
  • add NMIE_INIT config depend on CONFIG_SMRNMI
    • default open
    • when open : mnstatus.nmie init with 1 and allow to write 0
    • when close : align mnstatus.nmie behavior with the manual

* remove redundant assign code
* adjust some MUXDEF to IFDEF
* add NMIE_INIT config depend on CONFIG_SMRNMI
	* default open
	* when open : mnstatus.nmie init with 1 and allow to write 0
	* when close : align mnstatus.nmie behavior with the manual
@lewislzh lewislzh changed the title fix(format): adjust code format and add one config fix(format): adjust code format and add NMIE_INIT config Oct 25, 2024
@lewislzh lewislzh merged commit c1e2447 into master Oct 25, 2024
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@lewislzh lewislzh deleted the fix-dbltrp branch October 25, 2024 10:20
Tang-Haojin pushed a commit to OpenXiangShan/XiangShan that referenced this pull request Oct 29, 2024
* NEMU commit: 066cb1f1c61feb21153399c26ca393dfb3a560d7
* NEMU configs:
  * riscv64-xs-ref_defconfig
  * riscv64-dual-xs-ref_defconfig

Including:
  * fix(format): adjust code format and add one config (OpenXiangShan/NEMU#603)
  * fix(vfredusum): set xstatus.fs and xstatus.vs dirty (OpenXiangShan/NEMU#605)
  * fix(vf): do not set dirtyFs for some instructions (OpenXiangShan/NEMU#606)
  * feat(trigger): add trigger support for rva.
  * configs(xs): open Sm/sdbltrp extension and add MDT_INIT config (OpenXiangShan/NEMU#604)

---

* spike commit: c0b18d3913d8ceac83743a053a7dbd2fb8716c83
* spike config: CPU=XIANGSHAN

Including:
* fix(rva, trigger): For rva instr, raise BP from trigger prior to misaligned.
* fix(Makefile): Increase maxdepth for finding .h files.
* fix(tdata1): CPU_XIANGSHAN do not implement hit bit in tdata1.
* fix(icount): place the read before the return of the detect_icount_match.
Anzooooo pushed a commit to OpenXiangShan/XiangShan that referenced this pull request Oct 30, 2024
* NEMU commit: 066cb1f1c61feb21153399c26ca393dfb3a560d7
* NEMU configs:
  * riscv64-xs-ref_defconfig
  * riscv64-dual-xs-ref_defconfig

Including:
  * fix(format): adjust code format and add one config (OpenXiangShan/NEMU#603)
  * fix(vfredusum): set xstatus.fs and xstatus.vs dirty (OpenXiangShan/NEMU#605)
  * fix(vf): do not set dirtyFs for some instructions (OpenXiangShan/NEMU#606)
  * feat(trigger): add trigger support for rva.
  * configs(xs): open Sm/sdbltrp extension and add MDT_INIT config (OpenXiangShan/NEMU#604)

---

* spike commit: c0b18d3913d8ceac83743a053a7dbd2fb8716c83
* spike config: CPU=XIANGSHAN

Including:
* fix(rva, trigger): For rva instr, raise BP from trigger prior to misaligned.
* fix(Makefile): Increase maxdepth for finding .h files.
* fix(tdata1): CPU_XIANGSHAN do not implement hit bit in tdata1.
* fix(icount): place the read before the return of the detect_icount_match.
Tang-Haojin added a commit to OpenXiangShan/XiangShan that referenced this pull request Nov 21, 2024
* NEMU commit: 65b95cbb5d7c36f4d2cb38bfc0e1f6e43435f309
* NEMU configs:
    * riscv64-xs-ref_defconfig
    * riscv64-dual-xs-ref_defconfig

Including:
  * ci: enable ci for kunminghu-v2r2-930
* fix(lrsc): configure NEMU's reservation set size to 64B to match
XiangShan. (OpenXiangShan/NEMU#654)
* fix(gva): fix gva bit set/clear logic in mstatus/hstatus.
(OpenXiangShan/NEMU#642)
  * fix(exception): fix exception type raised in paddr_write.
  * fix(mmio): should use Logm instead of Log
  * fix(mmio): configure mmio space separately
* fix(aes): fix decode logic and exception check for aes64ks1i.
(OpenXiangShan/NEMU#646)
* fix(trap): fix the decoding of nemu_trap to make it consistent with
XiangShan. (OpenXiangShan/NEMU#639)
  * fix(zcmop): fix decode logic of c_mop (OpenXiangShan/NEMU#645)
* fix(rvv): set xstatus.vs dirty when execute vector int instructions
(OpenXiangShan/NEMU#631)
* fix(mmio): check mmio misalign only after confirming addr is an mmio
address.
  * fix(mip): use get_mip method replace mip->val
  * fix(csr, aia): add access siselect(vsiselect) in V mode
  * fix(flash): use mmap to create the io space (OpenXiangShan/NEMU#623)
* fix(fs, vs): fix check fs/vs when executing float/vector instr
(OpenXiangShan/NEMU#621)
  * fix(rvf): fix wrong patterns in the decoder (OpenXiangShan/NEMU#620)
* fix(build): extract .a files before running ar
(OpenXiangShan/NEMU#613)
* fix(device): init_flash should be called only once
(OpenXiangShan/NEMU#618)
* fix(store_queue): clear the queue when init_mem
(OpenXiangShan/NEMU#616)
* fix(ref): use uint64_t for the loop iterator (OpenXiangShan/NEMU#609)
* refactor: handle decode operations with appropriate macros
(OpenXiangShan/NEMU#601)
* fix(rvb): restore the decode table of zext.h (OpenXiangShan/NEMU#612)
  * fix(rvh): fix the decode logic of hsv.d (OpenXiangShan/NEMU#610)
* fix(vf): do not set dirtyFs for some instructions
(OpenXiangShan/NEMU#606)
* fix(vfredusum): set xstatus.fs and xstatus.vs dirty
(OpenXiangShan/NEMU#605)
* fix(format): adjust code format and add one config
(OpenXiangShan/NEMU#603)
* fix(csrrw): add legal write check for mstatus.mpp, mnstatus.mnpp,
hpmevent.optype and wmask for mhpmevent
  * fix(mhpmevent): add rtl guidance for mhpmevent.of logic
  * fix(mhpmevent): add CSRS_M_HPMEVENTS_STRUCT for mhpmevent csr.
  * fix(dbltrp): trap info update in raise_intr (OpenXiangShan/NEMU#596)
  * fix(tval): update cpu.instr when set-jmp (OpenXiangShan/NEMU#599)
* fix(vxred): set xstatus.fs or xstatus.vs dirty unconditionally
(OpenXiangShan/NEMU#598)
* fix(vf): vfclass should not set xstatus.FS to dirty
(OpenXiangShan/NEMU#595)
  * refactor: remove the macro __ICS_EXPORT (OpenXiangShan/NEMU#593)
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3 participants