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Merged
Tang-Haojin merged 3 commits into from
Oct 29, 2024
Merged

feat(Ss/Smdbltrp) : Support RISC-V Ss/Smdbltrp Extension #3789

Tang-Haojin merged 3 commits into from
Oct 29, 2024

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@lewislzh lewislzh commented Oct 28, 2024 •
edited by Tang-Haojin
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  • NEMU commit: 066cb1f1c61feb21153399c26ca393dfb3a560d7
  • NEMU configs:
    • riscv64-xs-ref_defconfig
    • riscv64-dual-xs-ref_defconfig

Including:

  • spike commit: c0b18d3913d8ceac83743a053a7dbd2fb8716c83
  • spike config: CPU=XIANGSHAN

Including:

  • fix(rva, trigger): For rva instr, raise BP from trigger prior to misaligned.
  • fix(Makefile): Increase maxdepth for finding .h files.
  • fix(tdata1): CPU_XIANGSHAN do not implement hit bit in tdata1.
  • fix(icount): place the read before the return of the detect_icount_match.

@lewislzh
feat(Ss/Smdbltrp) : Support RISC-V Ss/Smdbltrp Extension
262f2fb 
* Support Smdbltrp Extension
	* add MDT field to mstatus reg
	* support MDT to control MIE field
	* support double trap check in M mode
	* support double trap Handler to MNTrapEvent when nmie open
	* support xret to clear MDT field and return from double trap

* Support Ssdbltrp Extension
	* add DTE fiele to m/henvcfg reg
	* support DTE to control ss/vsdbltrp extension open
	* add SDT field to ss/vsstatus reg
	* support SDT to control SIE field
	* support double trap check in VS/S mode
	* support double trap handler to MTrapEvent
	* support xret to clear SDT field and return from double trap
@lewislzh lewislzh force-pushed the dev-dbltrp branch 3 times, most recently from c193a87 to 3dde216 Compare October 28, 2024 14:47
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XiangShanRobot commented Oct 28, 2024

[Generated by IPC robot]
commit: 3dde216

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
3dde216 1.928 0.450 2.699 1.189 2.823 2.460 2.395 0.913 1.373 1.611 3.418 2.742 2.420 3.263

master branch:

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
9a07878
c3d62b6 1.928 0.450 2.699 1.190 2.823 2.460 2.395 0.913 1.373 1.611 3.418 2.742 2.420 3.263
a6da536 1.917 0.450 2.699 1.204 2.823 2.460 2.395 0.913 1.373 1.611 3.418 2.742 2.420 3.263
b3c3582 1.928 0.450 2.699 1.190 2.823 2.460 2.395 0.913 1.373 1.611 3.418 2.742 2.420 3.263
faf7d50 1.928 0.450 2.699 1.195 2.823 2.460 2.395 0.913 1.373 1.611 3.418 2.742 2.420 3.263

@lewislzh
fix(sm/ssdbltrp) : fix xret and dbltrp handling logic, add reg init
0c06377 
	* fix xtvec generate logic when dbltrp happen
	* change the init val of vs/sstatus.SDT to zero
	* delete m/henvcfg addrinperf
	* fix xret/xTrapevent output field
	* fix xdt logic in xret
	* fix the logic of the dependency chain from DTE to xDT to xIE.
        * when nmie = 0, all exception and interrupt are disabled
	* add config mdtInit to init mdt
	* init xenvcfg.DTE to zero , as some software not support
	  ssdbltrp
@XiangShanRobot
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XiangShanRobot commented Oct 29, 2024

[Generated by IPC robot]
commit: 418adb6

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
418adb6 1.917 0.450 2.699 1.194 2.823 2.460 2.395 0.913 1.373 1.611 3.418 2.742 2.420 3.263

master branch:

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
189d8d0
fab276f 1.917 1.192 2.823 2.460 0.913 1.611 3.418 2.420 3.263
9a07878
c3d62b6 1.928 0.450 2.699 1.190 2.823 2.460 2.395 0.913 1.373 1.611 3.418 2.742 2.420 3.263
a6da536 1.917 0.450 2.699 1.204 2.823 2.460 2.395 0.913 1.373 1.611 3.418 2.742 2.420 3.263

@Tang-Haojin Tang-Haojin merged commit 6808b80 into master Oct 29, 2024
9 checks passed
@Tang-Haojin Tang-Haojin deleted the dev-dbltrp branch October 29, 2024 12:02
Anzooooo pushed a commit that referenced this pull request Oct 30, 2024
@lewislzh @Anzooooo
feat(Ss/Smdbltrp) : Support RISC-V Ss/Smdbltrp Extension (#3789)
b159d6e 
* NEMU commit: 066cb1f1c61feb21153399c26ca393dfb3a560d7
* NEMU configs:
  * riscv64-xs-ref_defconfig
  * riscv64-dual-xs-ref_defconfig

Including:
  * fix(format): adjust code format and add one config (OpenXiangShan/NEMU#603)
  * fix(vfredusum): set xstatus.fs and xstatus.vs dirty (OpenXiangShan/NEMU#605)
  * fix(vf): do not set dirtyFs for some instructions (OpenXiangShan/NEMU#606)
  * feat(trigger): add trigger support for rva.
  * configs(xs): open Sm/sdbltrp extension and add MDT_INIT config (OpenXiangShan/NEMU#604)

---

* spike commit: c0b18d3913d8ceac83743a053a7dbd2fb8716c83
* spike config: CPU=XIANGSHAN

Including:
* fix(rva, trigger): For rva instr, raise BP from trigger prior to misaligned.
* fix(Makefile): Increase maxdepth for finding .h files.
* fix(tdata1): CPU_XIANGSHAN do not implement hit bit in tdata1.
* fix(icount): place the read before the return of the detect_icount_match.
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@Tang-Haojin Tang-Haojin Tang-Haojin approved these changes

@huxuan0307 huxuan0307 Awaiting requested review from huxuan0307

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4 participants

@lewislzh @XiangShanRobot @Tang-Haojin