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optimize L1 DCache timing #616

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Merged
poemonsense merged 3 commits into from
Mar 1, 2021
Merged

optimize L1 DCache timing #616

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fb69dc4
DCache: remove ecc to improve timing.
njuallen Feb 28, 2021
1f2ce41
Merge branch 'master' of github.com:RISCVERS/XiangShan
njuallen Feb 28, 2021
55ea41c
MissQueue: refill_arb change RRArbiter to Arbiter to improve timing.
njuallen Feb 28, 2021
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4 changes: 2 additions & 2 deletions src/main/scala/xiangshan/XSCore.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -214,8 +214,8 @@ trait HasXSParameter {
)

val dcacheParameters = DCacheParameters(
tagECC = Some("secded"),
dataECC = Some("secded"),
tagECC = Some("none"),
dataECC = Some("none"),
nMissEntries = 16,
nProbeEntries = 16,
nReleaseEntries = 16,
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2 changes: 1 addition & 1 deletion src/main/scala/xiangshan/cache/MissQueue.scala
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Expand Up @@ -364,7 +364,7 @@ class MissQueue(edge: TLEdgeOut) extends DCacheModule with HasTLDump
})

val pipe_req_arb = Module(new RRArbiter(new MainPipeReq, cfg.nMissEntries))
val refill_arb = Module(new RRArbiter(new Refill, cfg.nMissEntries))
val refill_arb = Module(new Arbiter(new Refill, cfg.nMissEntries))

// dispatch req to MSHR
val primary_ready = Wire(Vec(cfg.nMissEntries, Bool()))
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