optimize L1 DCache timing #616
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poemonsense
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Mar 1, 2021
lewislzh
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Nov 1, 2024
Bump nemu ref in ready-to-run * NEMU commit: 861f8d3187fa8a58e14d2394d56b28f1f434adc2 * NEMU configs: * riscv64-xs-ref_defconfig * riscv64-dual-xs-ref_defconfig Including: * fix(dbltrp): No critical error is reported when comparing with Xiangshan. * feat(dev-zihintpause): add support for pause (#622) * fix(flash): use mmap to create the io space (#623) * fix(fs, vs): fix check fs/vs when executing float/vector instr (#621) * fix(rvf): fix wrong patterns in the decoder (#620) * feat(Zcb): support Zcb arithmetic instructions (#619) * fix(build): extract .a files before running ar (#613) * fix(device): init_flash should be called only once (#618) * fix(store_queue): clear the queue when init_mem (#616) * fix(ref): use uint64_t for the loop iterator (#609) * refactor: handle decode operations with appropriate macros (#601) * fix(rvb): restore the decode table of zext.h (#612) * fix(rvh): fix the decode logic of hsv.d (#610) Bump spike ref in ready-to-run * spike commit: 74f254ca17ab7bd3bc9e61be0ffd73bbdb1c732d * spike config: CPU=XIANGSHAN Including: * fix(sc): mcontrol6 addr trigger still match and fire for failed sc.
lewislzh
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Nov 1, 2024
Bump nemu ref in ready-to-run * NEMU commit: 861f8d3187fa8a58e14d2394d56b28f1f434adc2 * NEMU configs: * riscv64-xs-ref_defconfig * riscv64-dual-xs-ref_defconfig Including: * fix(dbltrp): No critical error is reported when comparing with Xiangshan. * feat(dev-zihintpause): add support for pause (#622) * fix(flash): use mmap to create the io space (#623) * fix(fs, vs): fix check fs/vs when executing float/vector instr (#621) * fix(rvf): fix wrong patterns in the decoder (#620) * feat(Zcb): support Zcb arithmetic instructions (#619) * fix(build): extract .a files before running ar (#613) * fix(device): init_flash should be called only once (#618) * fix(store_queue): clear the queue when init_mem (#616) * fix(ref): use uint64_t for the loop iterator (#609) * refactor: handle decode operations with appropriate macros (#601) * fix(rvb): restore the decode table of zext.h (#612) * fix(rvh): fix the decode logic of hsv.d (#610) Bump spike ref in ready-to-run * spike commit: 74f254ca17ab7bd3bc9e61be0ffd73bbdb1c732d * spike config: CPU=XIANGSHAN Including: * fix(sc): mcontrol6 addr trigger still match and fire for failed sc.
huxuan0307
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Nov 1, 2024
Bump nemu ref in ready-to-run * NEMU commit: 861f8d3187fa8a58e14d2394d56b28f1f434adc2 * NEMU configs: * riscv64-xs-ref_defconfig * riscv64-dual-xs-ref_defconfig Including: * fix(dbltrp): No critical error is reported when comparing with Xiangshan. * feat(dev-zihintpause): add support for pause (#622) * fix(flash): use mmap to create the io space (#623) * fix(fs, vs): fix check fs/vs when executing float/vector instr (#621) * fix(rvf): fix wrong patterns in the decoder (#620) * feat(Zcb): support Zcb arithmetic instructions (#619) * fix(build): extract .a files before running ar (#613) * fix(device): init_flash should be called only once (#618) * fix(store_queue): clear the queue when init_mem (#616) * fix(ref): use uint64_t for the loop iterator (#609) * refactor: handle decode operations with appropriate macros (#601) * fix(rvb): restore the decode table of zext.h (#612) * fix(rvh): fix the decode logic of hsv.d (#610) Bump spike ref in ready-to-run * spike commit: 74f254ca17ab7bd3bc9e61be0ffd73bbdb1c732d * spike config: CPU=XIANGSHAN Including: * fix(sc): mcontrol6 addr trigger still match and fire for failed sc.
Tang-Haojin
added a commit
that referenced
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Nov 20, 2024
* NEMU commit: 65b95cbb5d7c36f4d2cb38bfc0e1f6e43435f309
* NEMU configs:
* riscv64-xs-ref_defconfig
* riscv64-dual-xs-ref_defconfig
Including:
* ci: enable ci for kunminghu-v2r2-930
* fix(lrsc): configure NEMU's reservation set size to 64B to match XiangShan. (#654)
* fix(gva): fix gva bit set/clear logic in mstatus/hstatus. (#642)
* fix(exception): fix exception type raised in paddr_write.
* fix(mmio): should use Logm instead of Log
* fix(mmio): configure mmio space separately
* fix(aes): fix decode logic and exception check for aes64ks1i. (#646)
* fix(trap): fix the decoding of nemu_trap to make it consistent with XiangShan. (#639)
* fix(zcmop): fix decode logic of c_mop (#645)
* fix(rvv): set xstatus.vs dirty when execute vector int instructions (#631)
* fix(mmio): check mmio misalign only after confirming addr is an mmio address.
* fix(mip): use get_mip method replace mip->val
* fix(csr, aia): add access siselect(vsiselect) in V mode
* fix(flash): use mmap to create the io space (#623)
* fix(fs, vs): fix check fs/vs when executing float/vector instr (#621)
* fix(rvf): fix wrong patterns in the decoder (#620)
* fix(build): extract .a files before running ar (#613)
* fix(device): init_flash should be called only once (#618)
* fix(store_queue): clear the queue when init_mem (#616)
* fix(ref): use uint64_t for the loop iterator (#609)
* refactor: handle decode operations with appropriate macros (#601)
* fix(rvb): restore the decode table of zext.h (#612)
* fix(rvh): fix the decode logic of hsv.d (#610)
* fix(vf): do not set dirtyFs for some instructions (#606)
* fix(vfredusum): set xstatus.fs and xstatus.vs dirty (#605)
* fix(format): adjust code format and add one config (#603)
* fix(csrrw): add legal write check for mstatus.mpp, mnstatus.mnpp, hpmevent.optype and wmask for mhpmevent
* fix(mhpmevent): add rtl guidance for mhpmevent.of logic
* fix(mhpmevent): add CSRS_M_HPMEVENTS_STRUCT for mhpmevent csr.
* fix(dbltrp): trap info update in raise_intr (#596)
* fix(tval): update cpu.instr when set-jmp (#599)
* fix(vxred): set xstatus.fs or xstatus.vs dirty unconditionally (#598)
* fix(vf): vfclass should not set xstatus.FS to dirty (#595)
* refactor: remove the macro __ICS_EXPORT (#593)
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