LoadUnit: set TLB hit when the load has an exception #619
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ljwljwljwljw
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Mar 1, 2021
lewislzh
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Nov 1, 2024
Bump nemu ref in ready-to-run * NEMU commit: 861f8d3187fa8a58e14d2394d56b28f1f434adc2 * NEMU configs: * riscv64-xs-ref_defconfig * riscv64-dual-xs-ref_defconfig Including: * fix(dbltrp): No critical error is reported when comparing with Xiangshan. * feat(dev-zihintpause): add support for pause (#622) * fix(flash): use mmap to create the io space (#623) * fix(fs, vs): fix check fs/vs when executing float/vector instr (#621) * fix(rvf): fix wrong patterns in the decoder (#620) * feat(Zcb): support Zcb arithmetic instructions (#619) * fix(build): extract .a files before running ar (#613) * fix(device): init_flash should be called only once (#618) * fix(store_queue): clear the queue when init_mem (#616) * fix(ref): use uint64_t for the loop iterator (#609) * refactor: handle decode operations with appropriate macros (#601) * fix(rvb): restore the decode table of zext.h (#612) * fix(rvh): fix the decode logic of hsv.d (#610) Bump spike ref in ready-to-run * spike commit: 74f254ca17ab7bd3bc9e61be0ffd73bbdb1c732d * spike config: CPU=XIANGSHAN Including: * fix(sc): mcontrol6 addr trigger still match and fire for failed sc.
lewislzh
added a commit
that referenced
this pull request
Nov 1, 2024
Bump nemu ref in ready-to-run * NEMU commit: 861f8d3187fa8a58e14d2394d56b28f1f434adc2 * NEMU configs: * riscv64-xs-ref_defconfig * riscv64-dual-xs-ref_defconfig Including: * fix(dbltrp): No critical error is reported when comparing with Xiangshan. * feat(dev-zihintpause): add support for pause (#622) * fix(flash): use mmap to create the io space (#623) * fix(fs, vs): fix check fs/vs when executing float/vector instr (#621) * fix(rvf): fix wrong patterns in the decoder (#620) * feat(Zcb): support Zcb arithmetic instructions (#619) * fix(build): extract .a files before running ar (#613) * fix(device): init_flash should be called only once (#618) * fix(store_queue): clear the queue when init_mem (#616) * fix(ref): use uint64_t for the loop iterator (#609) * refactor: handle decode operations with appropriate macros (#601) * fix(rvb): restore the decode table of zext.h (#612) * fix(rvh): fix the decode logic of hsv.d (#610) Bump spike ref in ready-to-run * spike commit: 74f254ca17ab7bd3bc9e61be0ffd73bbdb1c732d * spike config: CPU=XIANGSHAN Including: * fix(sc): mcontrol6 addr trigger still match and fire for failed sc.
huxuan0307
pushed a commit
that referenced
this pull request
Nov 1, 2024
Bump nemu ref in ready-to-run * NEMU commit: 861f8d3187fa8a58e14d2394d56b28f1f434adc2 * NEMU configs: * riscv64-xs-ref_defconfig * riscv64-dual-xs-ref_defconfig Including: * fix(dbltrp): No critical error is reported when comparing with Xiangshan. * feat(dev-zihintpause): add support for pause (#622) * fix(flash): use mmap to create the io space (#623) * fix(fs, vs): fix check fs/vs when executing float/vector instr (#621) * fix(rvf): fix wrong patterns in the decoder (#620) * feat(Zcb): support Zcb arithmetic instructions (#619) * fix(build): extract .a files before running ar (#613) * fix(device): init_flash should be called only once (#618) * fix(store_queue): clear the queue when init_mem (#616) * fix(ref): use uint64_t for the loop iterator (#609) * refactor: handle decode operations with appropriate macros (#601) * fix(rvb): restore the decode table of zext.h (#612) * fix(rvh): fix the decode logic of hsv.d (#610) Bump spike ref in ready-to-run * spike commit: 74f254ca17ab7bd3bc9e61be0ffd73bbdb1c732d * spike config: CPU=XIANGSHAN Including: * fix(sc): mcontrol6 addr trigger still match and fire for failed sc.
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