please merge 'projutils' app (Nik's #410) for 2015.1 - thanks #412
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- Adds detailed documentation (FPGA, IP and user function level) about resources and power consumption during all the design phases - Enables Xilinx and Vivado mixed design flow
- support for export_simulation integration with generate_ip - support for 32bit new property on simset for axi-bfm - fixed issue with do file line feed - fixed issue with install path flow - support for xvhdl.nosort - filter ip dcp, txt, xml files
- fixed issue with the top library calculation by refactoring the code
…TclStore CR 815260 - Removed extra quotes from file variable, it interferes with file normalize
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