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please merge 'projutils' app (Nik's #410) for 2015.1 - thanks #412

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Merged
dbmccrohan merged 11 commits into from
Feb 27, 2015
Merged

please merge 'projutils' app (Nik's #410) for 2015.1 - thanks #412

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a1dc762
protoip revision 1.2
Feb 11, 2015
11a8cd4
update revision history for App XML File
Feb 11, 2015
c404b63
update legal.txt and tclIndex according to the requested actions for …
Feb 17, 2015
a773a4a
Merge commit 'refs/pull/405/head' of https://github.com/Xilinx/Xilinx…
dbmccrohan Feb 17, 2015
04f4892
Update catalog 2015.1 for pull request 405 (icl::protoip)
dbmccrohan Feb 17, 2015
ffe3b77
- support for -lib_map_path in exported script
rajklair Feb 20, 2015
0e9b2c5
Update catalog 2015.1 for pull request 407 (projutils,ies,modelsim,qu…
dbmccrohan Feb 23, 2015
18b0989
- fetch unique wcfg files from xsim.view property
rajklair Feb 24, 2015
4d362b3
Update catalog 2015.1 for pull request 409 (all sim apps)
dbmccrohan Feb 25, 2015
facecf9
Merge commit 'refs/pull/410/head' of https://github.com/Xilinx/Xilinx…
rajklair Feb 27, 2015
3bb3351
- removed extra quotes from file variable, it interferes with 'file n…
rajklair Feb 27, 2015
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4 changes: 2 additions & 2 deletions catalog/2015.1/icl/protoip/app.xml
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Expand Up @@ -2,10 +2,10 @@
<catalog>
<apps>
<app>
<revision_history>Adds support to Matlab interface. Enables ip_design_test and ip_prototype_test function to backup previous test results</revision_history>
<revision_history>Adds detailed documentation (FPGA, IP and user function level) about resources and power consumption during all the design phases. Enables Xilinx Vivado and Matlab mixed design flow</revision_history>
<name>protoip</name>
<pkg_require>Vivado 2014.4</pkg_require>
<author>asuardi &lt;&gt;</author>
<author>asuardi https://github.com/asuardi/</author>
<company>icl</company>
<company_display>Imperial College London</company_display>
<summary>Protoip is a utility for quickly prototyping C-based IP in FPGA hardware</summary>
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2 changes: 1 addition & 1 deletion catalog/2015.1/xilinx/ies/app.xml
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Expand Up @@ -2,7 +2,7 @@
<catalog>
<apps>
<app>
<revision_history>fixed lib map path to absolute for -absolute_path</revision_history>
<revision_history>refactored code to fix top-library fetching flow for manual mode</revision_history>
<name>ies</name>
<pkg_require>Vivado 2014.1</pkg_require>
<company>xilinx</company>
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2 changes: 1 addition & 1 deletion catalog/2015.1/xilinx/modelsim/app.xml
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Expand Up @@ -2,7 +2,7 @@
<catalog>
<apps>
<app>
<revision_history>fixed lib map path to absolute for -absolute_path</revision_history>
<revision_history>refactored code to fix top-library fetching flow for manual mode</revision_history>
<name>modelsim</name>
<pkg_require>Vivado 2014.1</pkg_require>
<company>xilinx</company>
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2 changes: 1 addition & 1 deletion catalog/2015.1/xilinx/projutils/app.xml
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Expand Up @@ -2,7 +2,7 @@
<catalog>
<apps>
<app>
<revision_history>wrap export_simulation under param and print info msg by default</revision_history>
<revision_history>support for the new directory structure for the IP generation</revision_history>
<name>projutils</name>
<pkg_require>Vivado 2014.1</pkg_require>
<company>xilinx</company>
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2 changes: 1 addition & 1 deletion catalog/2015.1/xilinx/questa/app.xml
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Expand Up @@ -2,7 +2,7 @@
<catalog>
<apps>
<app>
<revision_history>fixed lib map path to absolute for -absolute_path</revision_history>
<revision_history>refactored code to fix top-library fetching flow for manual mode</revision_history>
<name>questa</name>
<pkg_require>Vivado 2014.1</pkg_require>
<company>xilinx</company>
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2 changes: 1 addition & 1 deletion catalog/2015.1/xilinx/vcs/app.xml
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Expand Up @@ -2,7 +2,7 @@
<catalog>
<apps>
<app>
<revision_history>fixed lib map path to absolute for -absolute_path</revision_history>
<revision_history>refactored code to fix top-library fetching flow for manual mode</revision_history>
<name>vcs</name>
<pkg_require>Vivado 2014.1</pkg_require>
<company>xilinx</company>
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2 changes: 1 addition & 1 deletion catalog/2015.1/xilinx/xsim/app.xml
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Expand Up @@ -2,7 +2,7 @@
<catalog>
<apps>
<app>
<revision_history>do not extract files for XSim</revision_history>
<revision_history>fetch unique wcfg files from xsim.view to avoid xsim error</revision_history>
<name>xsim</name>
<pkg_require>Vivado 2014.1</pkg_require>
<company>xilinx</company>
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28 changes: 14 additions & 14 deletions catalog/catalog_2015.1.xml
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Expand Up @@ -33,8 +33,8 @@
<app>
<name>ies</name>
<company>xilinx</company>
<commit_id>5498d1de69ea1d50982cdba20fc9a6f7771db267</commit_id>
<revision>2.14</revision>
<commit_id>18b0989b9aa60b578790eb4e0ea5e561977ba962</commit_id>
<revision>2.16</revision>
</app>
<app>
<name>incrcompile</name>
Expand All @@ -51,8 +51,8 @@
<app>
<name>modelsim</name>
<company>xilinx</company>
<commit_id>5498d1de69ea1d50982cdba20fc9a6f7771db267</commit_id>
<revision>2.20</revision>
<commit_id>18b0989b9aa60b578790eb4e0ea5e561977ba962</commit_id>
<revision>2.22</revision>
</app>
<app>
<name>myapp</name>
Expand All @@ -69,20 +69,20 @@
<app>
<name>projutils</name>
<company>xilinx</company>
<commit_id>8733fde2f9dad30fc6d49c3b3776776cfbf236c2</commit_id>
<revision>3.16</revision>
<commit_id>ffe3b779fe4d49721fc647a26955b107e0fb943b</commit_id>
<revision>3.17</revision>
</app>
<app>
<name>protoip</name>
<company>icl</company>
<commit_id>7106498fdc53907051028bba2a63b656a8d02acd</commit_id>
<revision>1.1</revision>
<commit_id>a773a4a0bd63e0c2608962dcd2f81d3d7820430c</commit_id>
<revision>1.2</revision>
</app>
<app>
<name>questa</name>
<company>xilinx</company>
<commit_id>5498d1de69ea1d50982cdba20fc9a6f7771db267</commit_id>
<revision>1.11</revision>
<commit_id>18b0989b9aa60b578790eb4e0ea5e561977ba962</commit_id>
<revision>1.13</revision>
</app>
<app>
<name>riviera</name>
Expand Down Expand Up @@ -111,14 +111,14 @@
<app>
<name>vcs</name>
<company>xilinx</company>
<commit_id>5498d1de69ea1d50982cdba20fc9a6f7771db267</commit_id>
<revision>2.14</revision>
<commit_id>18b0989b9aa60b578790eb4e0ea5e561977ba962</commit_id>
<revision>2.16</revision>
</app>
<app>
<name>xsim</name>
<company>xilinx</company>
<commit_id>1517a5485bf5150d5e1bd2c3ef0d81a619c89e73</commit_id>
<revision>2.18</revision>
<commit_id>18b0989b9aa60b578790eb4e0ea5e561977ba962</commit_id>
<revision>2.20</revision>
</app>
</apps>
</catalog>
32 changes: 16 additions & 16 deletions tclapp/icl/protoip/README
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Expand Up @@ -7,27 +7,27 @@ All documentation for **protoip** is available in the Wiki at https://github.com

### protoip commands list (add -usage argument for usage instructions):

::tclapp::icl::protoip::make_template
::tclapp::icl::protoip::make_rand_stimuli
::tclapp::icl::protoip::ip_design_duplicate
::tclapp::icl::protoip::ip_design_delete
::tclapp::icl::protoip::ip_design_build
::tclapp::icl::protoip::ip_design_build_debug
::tclapp::icl::protoip::ip_design_test
::tclapp::icl::protoip::ip_design_test_debug
::tclapp::icl::protoip::ip_prototype_build
::tclapp::icl::protoip::ip_prototype_build_debug
::tclapp::icl::protoip::ip_prototype_load
::tclapp::icl::protoip::ip_prototype_load_debug
::tclapp::icl::protoip::ip_prototype_test
icl::protoip::make_template
icl::protoip::make_rand_stimuli
icl::protoip::ip_design_duplicate
icl::protoip::ip_design_delete
icl::protoip::ip_design_build
icl::protoip::ip_design_build_debug
icl::protoip::ip_design_test
icl::protoip::ip_design_test_debug
icl::protoip::ip_prototype_build
icl::protoip::ip_prototype_build_debug
icl::protoip::ip_prototype_load
icl::protoip::ip_prototype_load_debug
icl::protoip::ip_prototype_test


### using protoip form vivado


Vivado% package require ::tclapp::icl::prototip
Vivado% ::tclapp::icl::prototip::my_command1
Vivado% namespace import ::tclapp::icl::prototip::my_command1
Vivado% package require icl::prototip
Vivado% icl::prototip::my_command1
Vivado% namespace import icl::prototip::my_command1
Vivado% my_command1


4 changes: 2 additions & 2 deletions tclapp/icl/protoip/app.xml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2,10 +2,10 @@
<catalog>
<apps>
<app>
<revision_history>Adds support to Matlab interface. Enables ip_design_test and ip_prototype_test function to backup previous test results</revision_history>
<revision_history>Adds detailed documentation (FPGA, IP and user function level) about resources and power consumption during all the design phases. Enables Xilinx Vivado and Matlab mixed design flow</revision_history>
<name>protoip</name>
<pkg_require>Vivado 2014.4</pkg_require>
<author>asuardi &lt;&gt;</author>
<author>asuardi https://github.com/asuardi/</author>
<company>icl</company>
<company_display>Imperial College London</company_display>
<summary>Protoip is a utility for quickly prototyping C-based IP in FPGA hardware</summary>
Expand Down
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