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Merged
dpefour merged 43 commits into from
Sep 12, 2016
Merged

New version of Protoip on Xilinx Tcl Store #578

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c2bc28e
extended make_template
bulatkhusainov Feb 11, 2016
396a765
extended make_template with soc files generation
bulatkhusainov Feb 11, 2016
511373a
extended ip_design_build
bulatkhusainov Feb 11, 2016
3e499b8
ip_prototype_build extended
bulatkhusainov Feb 11, 2016
f271cd2
extended FPGAserver.h and main.c generation
bulatkhusainov Feb 11, 2016
2be6b61
extended soc echo.c generator
bulatkhusainov Feb 12, 2016
b7c2fe5
implemented soc_user.h and soc_user.c
bulatkhusainov Feb 13, 2016
f56cd81
implemented soc_prototype_load.tcl
bulatkhusainov Feb 13, 2016
2abf4fc
added FPGAclient genration files and HIL.m generation file
bulatkhusainov Feb 20, 2016
e683c8d
implemented soc_function with calling IP hardware
bulatkhusainov Feb 27, 2016
17d0993
fixed ethernet package lenghth bug
bulatkhusainov Feb 27, 2016
f2ff682
fixed floating point memcpy and added soc_prototype_load_debug
bulatkhusainov Mar 19, 2016
ef081ad
changes to make template
bulatkhusainov May 19, 2016
58da7fd
added soc_prototype to ip_design_delete function
bulatkhusainov May 20, 2016
4c148e7
add if structure to foo.cpp
bulatkhusainov Jun 11, 2016
d94b149
implemented soc_prototype_load_debug
bulatkhusainov Jun 13, 2016
88b4409
implemented automatic save of users code in soc_prototype_load_debug
bulatkhusainov Jun 13, 2016
7f83970
added possibility of disabling certan IP interfaces
bulatkhusainov Jun 15, 2016
e99cb8e
implemented copying sdk projects xml files in soc_prototype_load_debu…
bulatkhusainov Jul 5, 2016
4bd263e
added code for copying project settings in ip_design and ip_design_debug
bulatkhusainov Jul 12, 2016
90edfa4
added static specifier to foo.cpp interfaces and ap_cint library to f…
bulatkhusainov Jul 28, 2016
ac2a3f4
implemented adding information about SoC interfaces to ip_configurati…
bulatkhusainov Jul 28, 2016
6595b40
added soc_input and soc_output arguments to tcl make_template
bulatkhusainov Jul 28, 2016
6e04ffd
implemented saving soc related data in tcl and matlab flow. Checked t…
bulatkhusainov Jul 29, 2016
c6b6dac
minor corrections in soc_user.c and soc_user.h
bulatkhusainov Jul 29, 2016
52e9ffc
implemented TCP protocol for SoC function
bulatkhusainov Jul 30, 2016
c44143e
implemented wait when calling soc_prototype_load_debug
bulatkhusainov Jul 30, 2016
623b0c8
fixed closing projects in ip_prototype_load.tcl and soc_prototype_loa…
bulatkhusainov Jul 30, 2016
cd0c94f
modified make_template for handling both PL and SOC templates
bulatkhusainov Aug 2, 2016
5b096ee
implemented error checking for soc interface
bulatkhusainov Aug 2, 2016
c2e6a7f
Implemented soc_prototype_test in tcl design flow
bulatkhusainov Aug 2, 2016
3a80125
added soc_prototype_test.tcl
bulatkhusainov Aug 2, 2016
793e805
merged master and bulat_branch
bulatkhusainov Aug 4, 2016
e7f0c9c
Fixed the bug with saving HLS project parameters when duplicating pro…
bulatkhusainov Aug 29, 2016
4613013
added function help descriptions and fixed callinng matlab function f…
bulatkhusainov Aug 29, 2016
9323762
added Bulat to some license files and improved regression test
bulatkhusainov Aug 29, 2016
540b1b9
final preparations before pull request
bulatkhusainov Aug 29, 2016
4124221
Merge remote-tracking branch 'upstream/master'
bulatkhusainov Sep 10, 2016
ce0b1bd
updated documentaion of in doc folder for new commands
bulatkhusainov Sep 11, 2016
f3d22f0
updated documentaion of in doc folder for new commands(continued)
bulatkhusainov Sep 11, 2016
158aeb5
(re)generated app.xml, revision_history.txt and doc files
bulatkhusainov Sep 11, 2016
8568f35
minor changes in documentation
bulatkhusainov Sep 11, 2016
875b37d
Went through: How to Modify an existing app
bulatkhusainov Sep 11, 2016
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modified make_template for handling both PL and SOC templates
  • Loading branch information
@bulatkhusainov
bulatkhusainov committed Aug 2, 2016
commit cd0c94fc4bf98b8f3ec24d6f2e5a0eaaf754d192
167 changes: 88 additions & 79 deletions tclapp/icl/protoip/make_template.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -736,9 +736,11 @@ if {$error==0} {
file mkdir ip_prototype/build/prj

#added by Bulat
file mkdir soc_prototype/src
file mkdir soc_prototype/test/prj
file mkdir soc_prototype/test/results
if {$type_template == "SOC"} {
file mkdir soc_prototype/src
file mkdir soc_prototype/test/prj
file mkdir soc_prototype/test/results
}

#end added by Bulat

Expand Down Expand Up @@ -796,7 +798,7 @@ if {$error==0} {



if {$type_template == "PL"} {
if {$type_template == "PL" || $type_template == "SOC"} {


if {$count_is_fix==[expr $num_input_vectors+$num_output_vectors] || $count_is_float==[expr $num_input_vectors+$num_output_vectors]} {
Expand Down Expand Up @@ -833,20 +835,22 @@ if {$error==0} {


#added by Bulat
[::tclapp::icl::protoip::make_template::soc_make_main_c]
[::tclapp::icl::protoip::make_template::soc_make_echo_c $project_name]
[::tclapp::icl::protoip::make_template::soc_make_FPGAserver_h $project_name]

[::tclapp::icl::protoip::make_template::make_foo_function_wrapped $project_name]
[::tclapp::icl::protoip::make_template::make_soc_user $project_name]

#HIL test files
[::tclapp::icl::protoip::make_template::make_soc_FPGAclientAPI_h $project_name]
[::tclapp::icl::protoip::make_template::soc_FPGAclientMATLAB_m]
[::tclapp::icl::protoip::make_template::soc_FPGAclientMATLAB_c]
[::tclapp::icl::protoip::make_template::make_soc_test_HIL_m $project_name]
if {$type_template == "SOC"} {
[::tclapp::icl::protoip::make_template::soc_make_main_c]
[::tclapp::icl::protoip::make_template::soc_make_echo_c $project_name]
[::tclapp::icl::protoip::make_template::soc_make_FPGAserver_h $project_name]

[::tclapp::icl::protoip::make_template::make_foo_function_wrapped $project_name]
[::tclapp::icl::protoip::make_template::make_soc_user $project_name]

#HIL test files
[::tclapp::icl::protoip::make_template::make_soc_FPGAclientAPI_h $project_name]
[::tclapp::icl::protoip::make_template::soc_FPGAclientMATLAB_m]
[::tclapp::icl::protoip::make_template::soc_FPGAclientMATLAB_c]
[::tclapp::icl::protoip::make_template::make_soc_test_HIL_m $project_name]

[::tclapp::icl::protoip::make_template::make_build_soc_sdk_project_tcl]
[::tclapp::icl::protoip::make_template::make_build_soc_sdk_project_tcl]
}

#end added by Bulat

Expand Down Expand Up @@ -1032,12 +1036,13 @@ set type_template [lindex $args 18]
set type_design_flow [lindex $args 19]

#added by Bulat
set soc_input_vectors [lindex $args 20]
set soc_input_vectors_length [lindex $args 21]

set soc_output_vectors [lindex $args 22]
set soc_output_vectors_length [lindex $args 23]
if {$type_template == "SOC"} {
set soc_input_vectors [lindex $args 20]
set soc_input_vectors_length [lindex $args 21]

set soc_output_vectors [lindex $args 22]
set soc_output_vectors_length [lindex $args 23]
}
#end added by Bulat


Expand Down Expand Up @@ -1164,54 +1169,55 @@ puts $file "#type_design_flow"
puts $file $type_design_flow

#added by Bulat
if {$type_template == "SOC"} {
#soc_inputs:
puts $file "#soc_Input"

#soc_inputs:
puts $file "#soc_Input"

set count 0
foreach i $soc_input_vectors {
incr count
}
set count 0
foreach i $soc_input_vectors {
incr count
}

#Number of SOC inputs vectors
puts $file $count
set count 0
#Number of SOC inputs vectors
puts $file $count
set count 0

foreach i $soc_input_vectors {
#Vector name
puts $file $i
#Number of elements
puts $file [lindex $soc_input_vectors_length $count]
puts $file 0
puts $file 0
puts $file 0

incr count
}
foreach i $soc_input_vectors {
#Vector name
puts $file $i
#Number of elements
puts $file [lindex $soc_input_vectors_length $count]
puts $file 0
puts $file 0
puts $file 0
incr count
}


#soc_outputs:
puts $file "#soc_Output"
#soc_outputs:
puts $file "#soc_Output"

set count 0
foreach i $soc_output_vectors {
incr count
}
set count 0
foreach i $soc_output_vectors {
incr count
}

#Number of SOC output vectors
puts $file $count
set count 0
#Number of SOC output vectors
puts $file $count
set count 0

foreach i $soc_output_vectors {
#Vector name
puts $file $i
#Number of elements
puts $file [lindex $soc_output_vectors_length $count]
puts $file 0
puts $file 0
puts $file 0

incr count
foreach i $soc_output_vectors {
#Vector name
puts $file $i
#Number of elements
puts $file [lindex $soc_output_vectors_length $count]
puts $file 0
puts $file 0
puts $file 0

incr count
}
}

#end added by Bulat
Expand Down Expand Up @@ -5595,23 +5601,25 @@ set type_template [lindex $data [expr ($num_input_vectors * 5) + ($num_output_ve


#added by Bulat
set num_soc_input_vectors [lindex $data [expr [lsearch $data "#soc_Input"] + 1 ]]
set soc_input_vectors {}
set soc_input_vectors_length {}

for {set i 0} {$i < $num_soc_input_vectors} {incr i} {
lappend soc_input_vectors [lindex $data [expr [lsearch $data "#soc_Input"] + 2 + ($i * 5) ]]
lappend soc_input_vectors_length [lindex $data [expr [lsearch $data "#soc_Input"] + 3 + ($i * 5) ]]
}


set num_soc_output_vectors [lindex $data [expr [lsearch $data "#soc_Output"] + 1 ]]
set soc_output_vectors {}
set soc_output_vectors_length {}
if {$type_template == "SOC"} {
set num_soc_input_vectors [lindex $data [expr [lsearch $data "#soc_Input"] + 1 ]]
set soc_input_vectors {}
set soc_input_vectors_length {}

for {set i 0} {$i < $num_soc_output_vectors} {incr i} {
lappend soc_output_vectors [lindex $data [expr [lsearch $data "#soc_Output"] + 2 + ($i * 5) ]]
lappend soc_output_vectors_length [lindex $data [expr [lsearch $data "#soc_Output"] + 3 + ($i * 5) ]]
for {set i 0} {$i < $num_soc_input_vectors} {incr i} {
lappend soc_input_vectors [lindex $data [expr [lsearch $data "#soc_Input"] + 2 + ($i * 5) ]]
lappend soc_input_vectors_length [lindex $data [expr [lsearch $data "#soc_Input"] + 3 + ($i * 5) ]]
}


set num_soc_output_vectors [lindex $data [expr [lsearch $data "#soc_Output"] + 1 ]]
set soc_output_vectors {}
set soc_output_vectors_length {}

for {set i 0} {$i < $num_soc_output_vectors} {incr i} {
lappend soc_output_vectors [lindex $data [expr [lsearch $data "#soc_Output"] + 2 + ($i * 5) ]]
lappend soc_output_vectors_length [lindex $data [expr [lsearch $data "#soc_Output"] + 3 + ($i * 5) ]]
}
}
#end added by Bulat

Expand Down Expand Up @@ -5757,6 +5765,7 @@ foreach i $output_vectors {


#added by Bulat
if {$type_template == "SOC"} {
if { ([llength $soc_input_vectors]>0) && ([llength $soc_output_vectors]>0) } {
puts $file ""
puts $file ""
Expand Down Expand Up @@ -5786,7 +5795,7 @@ if { ([llength $soc_input_vectors]>0) && ([llength $soc_output_vectors]>0) } {
puts $file ""
puts $file ""
}

}
#end added by Bulat


Expand Down