New version of Protoip on Xilinx Tcl Store

tclapp/icl/protoip/app.xml

@@ -2,10 +2,10 @@
 <catalog>
   <apps>
     <app>
-      <revision_history>Bugs fixed: tcp/ip communication on server side, load xsdk workspace with ip_prototype_load_debug, download bitstream load</revision_history>
+      <revision_history>Added possibility of SoC prototyping (CPU and FPGA)</revision_history>
       <name>protoip</name>
       <pkg_require>Vivado 2015.1</pkg_require>
-      <author>asuardi https://github.com/asuardi/</author>
+      <author>Bulat Khusainov</author>
       <company>icl</company>
       <company_display>Imperial College London</company_display>
       <summary>Protoip is a utility for quickly prototyping C-based IP in FPGA hardware</summary>
@@ -49,7 +49,7 @@
         </proc>
         <proc>
           <name>ip_prototype_load_debug</name>
-          <summary>Compile the Vivado project according to the specification in [WORKING DIRECTORY]/design_parameters.tcl</summary>
+          <summary>Open SDK to debug the the FPGA Ethernet server running on the FPGA ARM processor.</summary>
         </proc>
         <proc>
           <name>ip_prototype_test</name>
@@ -63,6 +63,18 @@
           <name>make_template</name>
           <summary>Build the IP prototype project template in the current working directory</summary>
         </proc>
+        <proc>
+          <name>soc_prototype_load</name>
+          <summary>Build user&apos;s code (from soc_user.c and soc_user.h files) and the FPGA Ethernet server application using SDK according to the specification in [WORKING DIRECTORY]/design_parameters.tcl and program the FPGA. A connected evaluation board is required.</summary>
+        </proc>
+        <proc>
+          <name>soc_prototype_load_debug</name>
+          <summary>Open SDK to debug user&apos;s code (from soc_user.c and soc_user.h files) and the the FPGA Ethernet server running on the FPGA ARM processor.</summary>
+        </proc>
+        <proc>
+          <name>soc_prototype_test</name>
+          <summary>Run a test of the SOC named &apos;project_name&apos; according to the specification in [WORKING DIRECTORY]/doc/project_name/ip_configuration_parameters.txt. A connected evaluation board is required.</summary>
+        </proc>
       </procs>
     </app>
   </apps>

tclapp/icl/protoip/doc/legal.txt

@@ -13,6 +13,4 @@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 =================================================================================================
 This file must be included in <app>/doc/legal.txt for all accepted contributions to the Xilinx Tcl Store.
 All contributors must date and digitally sign once below in order to submit to the Xilinx Tcl Store
-<20141203 Date>::<asuardi>::<Andrea Suardi>
-=================================================================================================
-<20141203 Date>::<asuardi>::<Andrea Suardi>
+20160911::bulatkhusainov::Bulat Khusainov

tclapp/icl/protoip/doc/soc_prototype_load

@@ -0,0 +1,16 @@
+Description: 
+  Build user's code (from soc_user.c and soc_user.h files) and the FPGA Ethernet server application using SDK according 
+  to the project configuration parameters
+ [WORKING DIRECTORY]/doc/project_name/ip_configuration_parameters.txt
+  and program the FPGA.
+
+ An evaluation board connected to an host computer through an Ethernet and USB JTAG cable is required.
+
+ This command can be run after 'ip_prototype_build' command only.
+
+ Example:
+  soc_prototype_load -project_name my_project0 -board_name zedboard -type_eth udp
+  soc_prototype_load -project_name my_project0 -board_name zedboard -type_eth udp mem_base_address 33554432
+  soc_prototype_load -project_name my_project0 -board_name zedboard -type_eth udp -soc_input x_hat:8 -soc_output u_opt:28
+
+

tclapp/icl/protoip/doc/soc_prototype_load_debug

@@ -0,0 +1,7 @@
+ Description: 
+  Open SDK to debug user's code (from soc_user.c and soc_user.h files) and the the FPGA Ethernet server running on the FPGA ARM processor.
+
+  This command must be run after 'soc_prototype_load' command only.
+
+Example:
+  soc_prototype_load_debug -project_name my_project0 -board_name zedboard

tclapp/icl/protoip/doc/soc_prototype_test

@@ -0,0 +1,12 @@
+ Description: 
+  Run a HIL test of the SoC prototype named 'project_name'
+  according to the project configuration parameters
+ [WORKING DIRECTORY]/doc/project_name/ip_configuration_parameters.txt
+
+ An evaluation board connected to an host computer through an Ethernet cable is required.
+
+ This command must be run after 'soc_prototype_load' command only.
+
+
+ Example:
+  soc_prototype_test -project_name my_project0 -board_name zedboard -num_test 1

tclapp/icl/protoip/ip_design_build.tcl

@@ -83,6 +83,14 @@ proc ::tclapp::icl::protoip::ip_design_build::ip_design_build { args } {
     set returnString 0
 		set str_fix "fix"
 	set str_float "float"
+
+	#added by Bulat
+	set soc_input_vectors {}
+	set soc_input_vectors_length {}
+	set soc_output_vectors {}
+	set soc_output_vectors_length {}
+	#end added by Bulat
+
     while {[llength $args]} {
       set name [lshift args]
       switch -regexp -- $name {
@@ -418,6 +426,27 @@ if {$error==0} {
 			set type_test [lindex $data [expr ($num_input_vectors * 5) + ($num_output_vectors * 5) + 5 + 14]] 
 			set type_template [lindex $data [expr ($num_input_vectors * 5) + ($num_output_vectors * 5) + 5 + 16]]
 			set type_design_flow [lindex $data [expr ($num_input_vectors * 5) + ($num_output_vectors * 5) + 5 + 18]] 
+
+			#added by Bulat
+			set num_soc_input_vectors [lindex $data [expr [lsearch $data "#soc_Input"] + 1 ]]
+			set soc_input_vectors {}
+			set soc_input_vectors_length {}
+
+			for {set i 0} {$i < $num_soc_input_vectors} {incr i} {
+				lappend soc_input_vectors [lindex $data [expr [lsearch $data "#soc_Input"] + 2 + ($i * 5) ]]
+				lappend soc_input_vectors_length [lindex $data [expr [lsearch $data "#soc_Input"] + 3 + ($i * 5) ]]
+			}		
+
+
+			set num_soc_output_vectors [lindex $data [expr [lsearch $data "#soc_Output"] + 1 ]]
+			set soc_output_vectors {}
+			set soc_output_vectors_length {}
+
+			for {set i 0} {$i < $num_soc_output_vectors} {incr i} {
+				lappend soc_output_vectors [lindex $data [expr [lsearch $data "#soc_Output"] + 2 + ($i * 5) ]]
+				lappend soc_output_vectors_length [lindex $data [expr [lsearch $data "#soc_Output"] + 3 + ($i * 5) ]]
+			}
+			#end added by Bulat
 
 
 			# update configuration parameters
@@ -492,6 +521,10 @@ if {$error==0} {
 				incr m
 			}
 
+
+
+
+
 			set input_vectors $old_input_vectors 
 			set input_vectors_length $old_input_vectors_length 
 			set input_vectors_type $old_input_vectors_type 
@@ -525,7 +558,7 @@ if {$error==0} {
 
 			if {$count_is_fix==[expr $num_input_vectors+$num_output_vectors] || $count_is_float==[expr $num_input_vectors+$num_output_vectors]} {
 
-				[::tclapp::icl::protoip::make_template::make_project_configuration_parameters_dat $project_name $input_vectors $input_vectors_length $input_vectors_type $input_vectors_integer_length $input_vectors_fraction_length $output_vectors $output_vectors_length $output_vectors_type $output_vectors_integer_length $output_vectors_fraction_length $fclk $FPGA_name $board_name $type_eth $mem_base_address $num_test $type_test $type_template $type_design_flow]
+				[::tclapp::icl::protoip::make_template::make_project_configuration_parameters_dat $project_name $input_vectors $input_vectors_length $input_vectors_type $input_vectors_integer_length $input_vectors_fraction_length $output_vectors $output_vectors_length $output_vectors_type $output_vectors_integer_length $output_vectors_fraction_length $fclk $FPGA_name $board_name $type_eth $mem_base_address $num_test $type_test $type_template $type_design_flow $soc_input_vectors $soc_input_vectors_length $soc_output_vectors $soc_output_vectors_length]
 				[::tclapp::icl::protoip::make_template::make_ip_configuration_parameters_readme_txt $project_name]
 
 				# update ip_design/src/foo_data.h file

tclapp/icl/protoip/ip_design_build_debug.tcl

@@ -188,6 +188,29 @@ if {$error==0} {
 				append directives_to "../../src/" $project_name "_directives.tcl"
 				file copy -force  $directives_from $directives_to
 
+# added by Bulat
+
+				set source_file ""
+				append source_file $project_name "/.cproject"
+				set destination_file ""
+				append destination_file "../../src/.cproject"
+				file copy -force $source_file $destination_file
+
+				set source_file ""
+				append source_file $project_name "/.project"
+				set destination_file ""
+				append destination_file "../../src/.project"
+				file copy -force $source_file $destination_file
+
+				set source_file ""
+				append source_file $project_name "/vivado_hls.app"
+				set destination_file ""
+				append destination_file "../../src/vivado_hls.app"
+				file copy -force $source_file $destination_file
+
+
+#end added by Bulat
+
 
 				cd ../../../
 

tclapp/icl/protoip/ip_design_delete.tcl

@@ -236,6 +236,18 @@ if {$error==0} {
 			set filename ""
 			append filename ".metadata/" $project_name "_configuration_parameters.dat"
 			file delete -force $filename
+
+			#added by Bulat
+
+			set filename ""
+			append filename "soc_prototype/test/prj/" $project_name "." $board_name
+			file delete -force $filename
+
+			set filename ""
+			append filename "soc_prototype/test/results/" $project_name
+			file delete -force $filename
+
+			#end added by Bulat
 
 		}
 	}

tclapp/icl/protoip/ip_design_test.tcl

@@ -455,6 +455,27 @@ if {$error==0} {
 			set old_type_test [lindex $data [expr ($num_input_vectors * 5) + ($num_output_vectors * 5) + 5 + 14]] 
 			set type_template [lindex $data [expr ($num_input_vectors * 5) + ($num_output_vectors * 5) + 5 + 16]] 
 			set type_design_flow [lindex $data [expr ($num_input_vectors * 5) + ($num_output_vectors * 5) + 5 + 18]] 
+
+			#added by Bulat
+			set num_soc_input_vectors [lindex $data [expr [lsearch $data "#soc_Input"] + 1 ]]
+			set soc_input_vectors {}
+			set soc_input_vectors_length {}
+
+			for {set i 0} {$i < $num_soc_input_vectors} {incr i} {
+				lappend soc_input_vectors [lindex $data [expr [lsearch $data "#soc_Input"] + 2 + ($i * 5) ]]
+				lappend soc_input_vectors_length [lindex $data [expr [lsearch $data "#soc_Input"] + 3 + ($i * 5) ]]
+			}		
+
+
+			set num_soc_output_vectors [lindex $data [expr [lsearch $data "#soc_Output"] + 1 ]]
+			set soc_output_vectors {}
+			set soc_output_vectors_length {}
+
+			for {set i 0} {$i < $num_soc_output_vectors} {incr i} {
+				lappend soc_output_vectors [lindex $data [expr [lsearch $data "#soc_Output"] + 2 + ($i * 5) ]]
+				lappend soc_output_vectors_length [lindex $data [expr [lsearch $data "#soc_Output"] + 3 + ($i * 5) ]]
+			}
+			#end added by Bulat
 
 
 
@@ -573,7 +594,8 @@ if {$error==0} {
 			if {$count_is_fix==[expr $num_input_vectors+$num_output_vectors] || $count_is_float==[expr $num_input_vectors+$num_output_vectors]} {
 
 
-				[::tclapp::icl::protoip::make_template::make_project_configuration_parameters_dat $project_name $input_vectors $input_vectors_length $input_vectors_type $input_vectors_integer_length $input_vectors_fraction_length $output_vectors $output_vectors_length $output_vectors_type $output_vectors_integer_length $output_vectors_fraction_length $fclk $FPGA_name $board_name $type_eth $mem_base_address $num_test $type_test $type_template $type_design_flow]
+				#[::tclapp::icl::protoip::make_template::make_project_configuration_parameters_dat $project_name $input_vectors $input_vectors_length $input_vectors_type $input_vectors_integer_length $input_vectors_fraction_length $output_vectors $output_vectors_length $output_vectors_type $output_vectors_integer_length $output_vectors_fraction_length $fclk $FPGA_name $board_name $type_eth $mem_base_address $num_test $type_test $type_template $type_design_flow]
+				[::tclapp::icl::protoip::make_template::make_project_configuration_parameters_dat $project_name $input_vectors $input_vectors_length $input_vectors_type $input_vectors_integer_length $input_vectors_fraction_length $output_vectors $output_vectors_length $output_vectors_type $output_vectors_integer_length $output_vectors_fraction_length $fclk $FPGA_name $board_name $type_eth $mem_base_address $num_test $type_test $type_template $type_design_flow $soc_input_vectors $soc_input_vectors_length $soc_output_vectors $soc_output_vectors_length]
 
 				[::tclapp::icl::protoip::make_template::make_ip_configuration_parameters_readme_txt $project_name]
 

tclapp/icl/protoip/ip_prototype_build.tcl

@@ -230,6 +230,27 @@ if {$error==0} {
 			set type_template [lindex $data [expr ($num_input_vectors * 5) + ($num_output_vectors * 5) + 5 + 16]]
 			set type_design_flow [lindex $data [expr ($num_input_vectors * 5) + ($num_output_vectors * 5) + 5 + 18]] 
 
+			#added by Bulat
+			set num_soc_input_vectors [lindex $data [expr [lsearch $data "#soc_Input"] + 1 ]]
+			set soc_input_vectors {}
+			set soc_input_vectors_length {}
+
+			for {set i 0} {$i < $num_soc_input_vectors} {incr i} {
+				lappend soc_input_vectors [lindex $data [expr [lsearch $data "#soc_Input"] + 2 + ($i * 5) ]]
+				lappend soc_input_vectors_length [lindex $data [expr [lsearch $data "#soc_Input"] + 3 + ($i * 5) ]]
+			}		
+
+
+			set num_soc_output_vectors [lindex $data [expr [lsearch $data "#soc_Output"] + 1 ]]
+			set soc_output_vectors {}
+			set soc_output_vectors_length {}
+
+			for {set i 0} {$i < $num_soc_output_vectors} {incr i} {
+				lappend soc_output_vectors [lindex $data [expr [lsearch $data "#soc_Output"] + 2 + ($i * 5) ]]
+				lappend soc_output_vectors_length [lindex $data [expr [lsearch $data "#soc_Output"] + 3 + ($i * 5) ]]
+			}
+			#end added by Bulat
+
 
 			# update configuration parameters
 
@@ -277,7 +298,7 @@ if {$error==0} {
 
 
 
-			[::tclapp::icl::protoip::make_template::make_project_configuration_parameters_dat $project_name $input_vectors $input_vectors_length $input_vectors_type $input_vectors_integer_length $input_vectors_fraction_length $output_vectors $output_vectors_length $output_vectors_type $output_vectors_integer_length $output_vectors_fraction_length $fclk $FPGA_name $board_name $type_eth $mem_base_address $num_test $type_test $type_template $type_design_flow]
+			[::tclapp::icl::protoip::make_template::make_project_configuration_parameters_dat $project_name $input_vectors $input_vectors_length $input_vectors_type $input_vectors_integer_length $input_vectors_fraction_length $output_vectors $output_vectors_length $output_vectors_type $output_vectors_integer_length $output_vectors_fraction_length $fclk $FPGA_name $board_name $type_eth $mem_base_address $num_test $type_test $type_template $type_design_flow $soc_input_vectors $soc_input_vectors_length $soc_output_vectors $soc_output_vectors_length]
 			##make configuration parameters readme
 			[::tclapp::icl::protoip::make_template::make_ip_configuration_parameters_readme_txt $project_name]
 

tclapp/icl/protoip/ip_prototype_load.tcl

@@ -238,6 +238,27 @@ if {$error==0} {
 			set type_template [lindex $data [expr ($num_input_vectors * 5) + ($num_output_vectors * 5) + 5 + 16]]
 			set type_design_flow [lindex $data [expr ($num_input_vectors * 5) + ($num_output_vectors * 5) + 5 + 18]] 
 
+			#added by Bulat
+			set num_soc_input_vectors [lindex $data [expr [lsearch $data "#soc_Input"] + 1 ]]
+			set soc_input_vectors {}
+			set soc_input_vectors_length {}
+
+			for {set i 0} {$i < $num_soc_input_vectors} {incr i} {
+				lappend soc_input_vectors [lindex $data [expr [lsearch $data "#soc_Input"] + 2 + ($i * 5) ]]
+				lappend soc_input_vectors_length [lindex $data [expr [lsearch $data "#soc_Input"] + 3 + ($i * 5) ]]
+			}		
+
+
+			set num_soc_output_vectors [lindex $data [expr [lsearch $data "#soc_Output"] + 1 ]]
+			set soc_output_vectors {}
+			set soc_output_vectors_length {}
+
+			for {set i 0} {$i < $num_soc_output_vectors} {incr i} {
+				lappend soc_output_vectors [lindex $data [expr [lsearch $data "#soc_Output"] + 2 + ($i * 5) ]]
+				lappend soc_output_vectors_length [lindex $data [expr [lsearch $data "#soc_Output"] + 3 + ($i * 5) ]]
+			}
+			#end added by Bulat
+
 
 
 
@@ -309,7 +330,7 @@ if {$error==0} {
 
 			} else {
 
-			[::tclapp::icl::protoip::make_template::make_project_configuration_parameters_dat $project_name $input_vectors $input_vectors_length $input_vectors_type $input_vectors_integer_length $input_vectors_fraction_length $output_vectors $output_vectors_length $output_vectors_type $output_vectors_integer_length $output_vectors_fraction_length $fclk $FPGA_name $board_name $type_eth $mem_base_address $num_test $type_test $type_template $type_design_flow]
+			[::tclapp::icl::protoip::make_template::make_project_configuration_parameters_dat $project_name $input_vectors $input_vectors_length $input_vectors_type $input_vectors_integer_length $input_vectors_fraction_length $output_vectors $output_vectors_length $output_vectors_type $output_vectors_integer_length $output_vectors_fraction_length $fclk $FPGA_name $board_name $type_eth $mem_base_address $num_test $type_test $type_template $type_design_flow $soc_input_vectors $soc_input_vectors_length $soc_output_vectors $soc_output_vectors_length]
 			[::tclapp::icl::protoip::make_template::make_ip_configuration_parameters_readme_txt $project_name]
 
 			# update ip_design/src/FPGAclientAPI.h file
@@ -337,20 +358,21 @@ if {$error==0} {
 			# Create SDK Project
 			puts "Calling SDK to build the software project ..."
 
-			set sdk_p [open "|xsct build_sdk_project.tcl" r]
+			set sdk_p [open "|xsct build_sdk_project.tcl" r+]
 			while {![eof $sdk_p]} { gets $sdk_p line ; puts $line }
 			close $sdk_p
 
 			# set sdk_exit_flag=0 if error, sdk_exit_flag=1 if NOT error
 			set sdk_exit_flag [file exists workspace1/test_fpga/Release/test_fpga.elf]
 
+			puts "Bulat deug line4"
 
 			set error 0
 			if {$sdk_exit_flag==1}  {
 				puts ""
 				puts "Programming the FPGA ..."
 
-				set xmd_p [open "|xmd -tcl run_fpga_prototype.tcl" r]
+				set xmd_p [open "|xmd -tcl run_fpga_prototype.tcl" r+]
 				while {![eof $xmd_p]} { gets $xmd_p line ; puts $line }
 				close $xmd_p
 				after 5000

tclapp/icl/protoip/ip_prototype_load_debug.tcl

@@ -11,7 +11,7 @@ namespace eval ::tclapp::icl::protoip {
 
 proc ::tclapp::icl::protoip::ip_prototype_load_debug {args} {
 
-	  # Summary: Compile the Vivado project according to the specification in [WORKING DIRECTORY]/design_parameters.tcl
+	  # Summary: Open SDK to debug the the FPGA Ethernet server running on the FPGA ARM processor.
 
 	  # Argument Usage:
 	  # -project_name <arg>: Project name