Skip to content
Merged
Prev Previous commit
Next Next commit
Remove some unnecessarily aggressive asserts
  • Loading branch information
jakobbotsch committed Mar 20, 2024
commit 40d998ace1c7377b89579e5ad47ec86f3b7a9f96
9 changes: 0 additions & 9 deletions src/coreclr/jit/scopeinfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1721,8 +1721,6 @@ void CodeGen::psiBegProlog()
regNumber otherRegNum = REG_NA;
for (unsigned nCnt = 0; nCnt < structDesc.eightByteCount; nCnt++)
{
var_types regType = TYP_UNDEF;

if (nCnt == 0)
{
regNum = lclVarDsc->GetArgReg();
Expand All @@ -1735,12 +1733,6 @@ void CodeGen::psiBegProlog()
{
assert(false && "Invalid eightbyte number.");
}

regType = compiler->GetEightByteType(structDesc, nCnt);
#ifdef DEBUG
regType = compiler->mangleVarArgsType(regType);
assert(genMapRegNumToRegArgNum((nCnt == 0 ? regNum : otherRegNum), regType) != (unsigned)-1);
#endif // DEBUG
Comment on lines -1738 to -1743
Copy link
Member Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I have removed this assert in a couple of places because I don't think it is asserting anything meaningful. The existence and mapping of genMapRegNumToRegArgNum is really an internal detail of how genFnPrologCalleeRegArgs works, and I expect to be able to remove it once that function is rewritten.

}

varLocation.storeVariableInRegisters(regNum, otherRegNum);
Expand Down Expand Up @@ -1789,7 +1781,6 @@ void CodeGen::psiBegProlog()
regType = lclVarDsc->GetHfaType();
}
#endif // defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
assert(genMapRegNumToRegArgNum(lclVarDsc->GetArgReg(), regType) != (unsigned)-1);
#endif // DEBUG
varLocation.storeVariableInRegisters(lclVarDsc->GetArgReg(), REG_NA);
}
Expand Down