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0848153
Checkpoint
imhameed Feb 17, 2021
706cf0e
Add some shifts
imhameed Mar 5, 2021
79514da
Implement rounding
imhameed Mar 5, 2021
6cc2596
Implement ReverseElement{Bits,8,16,32}
imhameed Mar 5, 2021
f0e2e41
Add reciprocal fp/u32 operations
imhameed Mar 5, 2021
cca921b
Add some bitwise operations
imhameed Mar 5, 2021
dad5fed
Add negation
imhameed Mar 5, 2021
6341449
Add every AdvSimd symbol name
imhameed Mar 5, 2021
8580569
Minor cleanup
imhameed Mar 6, 2021
a9bc75e
Checkpoint
imhameed Mar 6, 2021
8d16907
Implement some multiplication ops
imhameed Mar 6, 2021
e5a6b06
Fix amd64
imhameed Mar 6, 2021
19cbca8
More multiplication
imhameed Mar 6, 2021
6a88dc7
Implement min/max
imhameed Mar 6, 2021
a82ad4d
Add load ops
imhameed Mar 6, 2021
5203566
Add clz/cls
imhameed Mar 6, 2021
da21e6f
Implement insert/insertscalar
imhameed Mar 6, 2021
94b7396
Add fused ops
imhameed Mar 6, 2021
0c5047c
Add extract
imhameed Mar 7, 2021
fabeff7
Add duplicate
imhameed Mar 7, 2021
8d5e824
Add divide
imhameed Mar 7, 2021
030032a
Add f32->{u32,i32}
imhameed Mar 7, 2021
069bebb
Add fp64->{u64,i64}
imhameed Mar 7, 2021
9788f4a
arm64 fp conversions
imhameed Mar 7, 2021
fc6f373
Add comparisons
imhameed Mar 7, 2021
07a7bff
Implement ceiling
imhameed Mar 7, 2021
f8594f7
Revert some stray unrelated changes
imhameed Mar 7, 2021
f37685d
Implement more bitwise operations
imhameed Mar 7, 2021
e666083
More arithmetic
imhameed Mar 7, 2021
5ebdb81
Implement Abs.*, Absolute.*
imhameed Mar 7, 2021
b20631f
Implement AbsoluteCompare.*
imhameed Mar 7, 2021
4a78abe
Misc fixes to shifts, math
imhameed Mar 7, 2021
d5ab5ec
Implement missing stuff from AdvSimd.Arm64
imhameed Mar 8, 2021
9e9adab
Implement the AdvSimd.Arm64 parts of fma
imhameed Mar 8, 2021
6560bd2
More AdvSimd.Arm64
imhameed Mar 8, 2021
5c60c8f
Implement ExtractVector64/ExtractVector128
imhameed Mar 8, 2021
16a4f7c
Unroll instructions with immediate constants and no fallback support …
imhameed Mar 8, 2021
643d6a4
... Fix MinPairwiseScalar/MinAcross/MaxPairwiseScalar/MaxAcross
imhameed Mar 9, 2021
76d24b6
Fix brain-os for ld1/st1
imhameed Mar 9, 2021
aa657a8
???
imhameed Mar 9, 2021
e526dc6
Fix floating point Add/Subtract
imhameed Mar 9, 2021
e95199d
Fix CompareEqualScalar/CompareGreaterThanOrEqualScalar/CompareGreater…
imhameed Mar 9, 2021
c94c07b
Fix ShiftRightArithmeticRounded, ShiftRightArithmeticRoundedScalar, S…
imhameed Mar 9, 2021
3d81808
Fix MultiplyDoublingWideningLowerAndSubtractSaturate, FusedMultiplySu…
imhameed Mar 9, 2021
d81b1f0
Fix ShiftLogicalSaturateScalar, ShiftArithmeticRoundedSaturateScalar,…
imhameed Mar 9, 2021
e69386d
Fix ShiftLeftLogicalSaturateUnsignedScalar, ShiftLogicalRoundedSatura…
imhameed Mar 9, 2021
5b49456
Fix PopCount
imhameed Mar 9, 2021
f31aec1
Fix ReverseElement8, ReverseElement16, ReverseElement32
imhameed Mar 9, 2021
12fd7c9
Fix ExtractNarrowingSaturateScalar, ExtractNarrowingSaturateUnsignedS…
imhameed Mar 9, 2021
d229944
More test fixes:
imhameed Mar 10, 2021
5baa928
LoadAndReplicateToVector: coerce the source pointer to the element ty…
imhameed Mar 10, 2021
0d67d57
Move OP_INSERT_* and OP_XCAST to a shared arm64/amd64 region
imhameed Mar 10, 2021
b14fc9a
Address feedback: move IntrinsicId (and another LLVM-only anonymous e…
imhameed Mar 10, 2021
059bce5
Don't attempt to scalarize a non-scalar sqshlu
imhameed Mar 10, 2021
bd2e5b2
MultiplyDoublingWideningSaturateScalar etc.: consistently place the s…
imhameed Mar 10, 2021
ca728df
Explicitly zero out the unused bits in scalar ops built out of vector…
imhameed Mar 10, 2021
24a89e1
Fix the vector concatenation overloads of Vector128/256
imhameed Mar 10, 2021
14602df
Sha1.FixedRotate is a scalar-in-vector op. TODO: refactor to use XOP_…
imhameed Mar 11, 2021
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Fix the vector concatenation overloads of Vector128/256
  • Loading branch information
imhameed committed Mar 11, 2021
commit 24a89e1478b73704aafb73f9b8d41a846673e2b5
4 changes: 4 additions & 0 deletions src/mono/mono/mini/mini-llvm.c
Original file line number Diff line number Diff line change
Expand Up @@ -7550,6 +7550,10 @@ process_bb (EmitContext *ctx, MonoBasicBlock *bb)
values [ins->dreg] = LLVMBuildBitCast (builder, lhs, t, "");
break;
}
case OP_XCONCAT: {
values [ins->dreg] = concatenate_vectors (ctx, lhs, rhs);
break;
}
#endif // defined(TARGET_X86) || defined(TARGET_AMD64) || defined(TARGET_ARM64) || defined(TARGET_WASM)

#if defined(TARGET_X86) || defined(TARGET_AMD64) || defined(TARGET_WASM)
Expand Down
2 changes: 2 additions & 0 deletions src/mono/mono/mini/mini-ops.h
Original file line number Diff line number Diff line change
Expand Up @@ -1565,6 +1565,8 @@ MINI_OP(OP_XOP_OVR_SCALAR_X_X_X, "xop_ovr_scalar_x_x_x", XREG, XREG, XREG)
MINI_OP3(OP_XOP_OVR_SCALAR_X_X_X_X, "xop_ovr_scalar_x_x_x_x", XREG, XREG, XREG, XREG)
MINI_OP(OP_XOP_OVR_BYSCALAR_X_X_X, "xop_ovr_byscalar_x_x_x", XREG, XREG, XREG)

MINI_OP(OP_XCONCAT, "xconcat", XREG, XREG, XREG)

MINI_OP(OP_XCAST, "xcast", XREG, XREG, NONE)
/* Extract element of vector */
/* The index is assumed to be in range */
Expand Down
36 changes: 35 additions & 1 deletion src/mono/mono/mini/simd-intrinsics.c
Original file line number Diff line number Diff line change
Expand Up @@ -257,6 +257,15 @@ emit_xcompare (MonoCompile *cfg, MonoClass *klass, MonoTypeEnum etype, MonoInst
return ins;
}

static gboolean
is_intrinsics_vector_type (MonoType *vector_type)
{
if (vector_type->type != MONO_TYPE_GENERICINST) return FALSE;
MonoClass *klass = mono_class_from_mono_type_internal (vector_type);
const char *name = m_class_get_name (klass);
return !strcmp (name, "Vector64`1") || !strcmp (name, "Vector128`1") || !strcmp (name, "Vector256`1");
}

static MonoType*
get_vector_t_elem_type (MonoType *vector_type)
{
Expand Down Expand Up @@ -487,6 +496,28 @@ static guint16 sri_vector_methods [] = {
SN_CreateScalarUnsafe,
};

static gboolean
is_elementwise_create_overload (MonoMethodSignature *fsig, MonoType *ret_type)
{
uint16_t param_count = fsig->param_count;
if (param_count < 1) return FALSE;
MonoType *type = fsig->params [0];
gboolean is_vector_primitive = MONO_TYPE_IS_PRIMITIVE (type) && (type->type >= MONO_TYPE_I1 && type->type <= MONO_TYPE_R8);
if (!is_vector_primitive) return FALSE;
if (!mono_metadata_type_equal (ret_type, type)) return FALSE;
for (uint16_t i = 1; i < param_count; ++i)
if (!mono_metadata_type_equal (type, fsig->params [i])) return FALSE;
return TRUE;
}

static gboolean
is_create_from_half_vectors_overload (MonoMethodSignature *fsig)
{
if (fsig->param_count != 2) return FALSE;
if (!is_intrinsics_vector_type (fsig->params [0])) return FALSE;
return mono_metadata_type_equal (fsig->params [0], fsig->params [1]);
}

static MonoInst*
emit_sri_vector (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
{
Expand Down Expand Up @@ -519,8 +550,11 @@ emit_sri_vector (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsi
MonoType *etype = get_vector_t_elem_type (fsig->ret);
if (fsig->param_count == 1 && mono_metadata_type_equal (fsig->params [0], etype))
return emit_simd_ins (cfg, klass, type_to_expand_op (etype), args [0]->dreg, -1);
else
else if (is_create_from_half_vectors_overload (fsig))
return emit_simd_ins (cfg, klass, OP_XCONCAT, args [0]->dreg, args [1]->dreg);
else if (is_elementwise_create_overload (fsig, etype))
return emit_vector_create_elementwise (cfg, fsig, fsig->ret, etype, args);
break;
}
case SN_CreateScalarUnsafe:
return emit_simd_ins_for_sig (cfg, klass, OP_CREATE_SCALAR_UNSAFE, -1, arg0_type, fsig, args);
Expand Down