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7aca5dc
Initial work
TIHan Dec 16, 2021
2752913
Added a comma to display
TIHan Dec 16, 2021
526e6c8
Cleanup
TIHan Dec 16, 2021
d850426
Fixing build
TIHan Dec 17, 2021
0ee6450
More cleanup
TIHan Dec 17, 2021
cb5a82e
Update comment
TIHan Dec 17, 2021
6ae9a94
Update comment
TIHan Dec 17, 2021
5c1997f
Added CompareEqual Vector64/128 with Zero tests
TIHan Jan 4, 2022
b33c72c
Merge remote-tracking branch 'upstream/main' into vector-64-128-zero-…
TIHan Jan 4, 2022
fd19fdc
Do not contain op1 for now
TIHan Jan 4, 2022
178ff52
Wrong intrinsic id used
TIHan Jan 5, 2022
c0a23c0
Removing generated tests
TIHan Jan 6, 2022
ad780ea
Removing generated tests
TIHan Jan 6, 2022
83c26ab
Added CompareEqual tests
TIHan Jan 6, 2022
9f7e7da
Supporting containment for first operand
TIHan Jan 6, 2022
1e67415
Fix test build
TIHan Jan 6, 2022
25b9d92
Passing correct register
TIHan Jan 6, 2022
c0dc7e4
Check IsVectorZero before not allocing a register
TIHan Jan 7, 2022
a718944
Update comment
TIHan Jan 7, 2022
1f45fa2
Fixing test
TIHan Jan 7, 2022
cb872da
Minor format change
TIHan Jan 7, 2022
c0708d7
Fixed formatting
TIHan Jan 7, 2022
bf49d11
Renamed test
TIHan Jan 8, 2022
bc7a557
Adding AdvSimd_Arm64 tests:
TIHan Jan 10, 2022
5939f36
Adding support for rest of 'cmeq' and 'fcmeq' instructions
TIHan Jan 10, 2022
6cd0ea8
Removing github csproj
TIHan Jan 10, 2022
2b30421
Minor test fix
TIHan Jan 10, 2022
0828de6
Fixed tests
TIHan Jan 10, 2022
fa43d19
Fix print
TIHan Jan 10, 2022
911f929
Minor format change
TIHan Jan 10, 2022
b91be1e
Fixing test
TIHan Jan 11, 2022
760a08c
Initial commit for Vector.Create to Vector.Zero normalization
TIHan Jan 14, 2022
c1a90b4
Added some emitter tests
TIHan Jan 18, 2022
32f86c1
Feedback
TIHan Jan 19, 2022
b08f552
Update emitarm64.cpp
TIHan Jan 19, 2022
c89e47b
Feedback
TIHan Jan 19, 2022
956e50a
Merge branch 'vector-64-128-zero-arm64-opts1' of github.com:TIHan/run…
TIHan Jan 19, 2022
2b526c9
Merge remote-tracking branch 'upstream' into vector-64-128-zero-arm64…
TIHan Jan 19, 2022
d51a988
Merge branch 'vector-64-128-zero-arm64-opts1' into vector-64-128-256-…
TIHan Jan 19, 2022
77c3d25
Merge remote-tracking branch 'upstream' into vector-64-128-256-Create…
TIHan Jan 20, 2022
b1065e8
Handling variations of Vector.Create
TIHan Jan 20, 2022
451f8e3
Use Operands iterator instead of edges
TIHan Jan 20, 2022
e231131
Fix condition
TIHan Jan 20, 2022
64ad95f
Simplify
TIHan Jan 20, 2022
333fc67
format
TIHan Jan 20, 2022
bc02904
Fixed IsFloatPositiveZero
TIHan Jan 21, 2022
d8c39e3
Uncomment
TIHan Jan 21, 2022
a5e51d5
Merging
TIHan Jan 21, 2022
38d9e7e
Updated tests to include Vector64.Create/Vector128.Create for ARM64
TIHan Jan 21, 2022
fb6047c
Making implementation of IsFloatPositiveZero explicit
TIHan Jan 21, 2022
bc1b9f4
Update src/coreclr/jit/gentree.cpp
TIHan Jan 24, 2022
d7904b6
Feedback
TIHan Jan 24, 2022
dbe1990
Merged
TIHan Jan 24, 2022
5b7d991
Update comment
TIHan Jan 24, 2022
5a7f674
Update comment
TIHan Jan 24, 2022
377b794
Do not perform optimization when VN CSE phase
TIHan Jan 24, 2022
1cf0b32
use ResetHWIntrinsicId
TIHan Jan 25, 2022
84f51cd
Assert !optValnumCSE_phase
TIHan Jan 25, 2022
31cd50d
Simplify IsVectorZero
TIHan Jan 25, 2022
383f147
Simplify IsVectorZero
TIHan Jan 25, 2022
29fb977
Simplify some uses of Vector*_get_Zero
TIHan Jan 25, 2022
51eae5a
Added another test
TIHan Jan 25, 2022
7d06ebf
Fixed formatting
TIHan Jan 25, 2022
177cd53
Revert lowering removal
TIHan Jan 25, 2022
32ac1fc
Merge remote-tracking branch 'upstream/main' into vector-64-128-256-C…
TIHan Feb 7, 2022
feed738
Initial work for optimizations on VectorZero value numbering
TIHan Feb 8, 2022
9840c5b
Allowing all Vector.Zero to be constant prop'ed. Added VNFuncSimdType…
TIHan Feb 8, 2022
36c4001
Update gentree.h
TIHan Feb 8, 2022
fc28677
Merge branch 'vector-64-128-256-Create-to-get_Zero' into vec-zero-vn
TIHan Feb 8, 2022
b074f09
Quick rename
TIHan Feb 8, 2022
2331a6e
Removed extra variable
TIHan Feb 8, 2022
f0d1ecc
Added default case
TIHan Feb 8, 2022
b15036f
Format
TIHan Feb 8, 2022
d27d877
Fixed vnDumpSimdType to take into account CorInfoType
TIHan Feb 9, 2022
e48ad65
Fixed gtNewSimdZeroNode to produce the right Vector*_get_Zero based o…
TIHan Feb 9, 2022
da48e4e
Formatting
TIHan Feb 10, 2022
3785e34
Feedback and a loop test
TIHan Feb 11, 2022
2b108d2
Added another test. Formatting fixes
TIHan Feb 11, 2022
b1c44cf
Added GetSimdBaseJitPreciseType
TIHan Feb 11, 2022
014b09f
Feedback
TIHan Feb 11, 2022
bb58117
Minor fix
TIHan Feb 11, 2022
7aae73b
Minor comment update
TIHan Feb 11, 2022
423d25a
Added another comment
TIHan Feb 11, 2022
616bb9b
Added another comment
TIHan Feb 11, 2022
84d3a94
Added another comment
TIHan Feb 11, 2022
ac3b474
Update comment
TIHan Feb 11, 2022
2769740
Formatting
TIHan Feb 11, 2022
92df1fd
Merge remote-tracking branch 'upstream/main' into vec-zero-vn
TIHan Feb 13, 2022
4a6d9a2
Feedback
TIHan Feb 14, 2022
2d6f367
Fixing build
TIHan Feb 14, 2022
759e8c0
Feedback
TIHan Feb 16, 2022
4c0f768
Merge remote-tracking branch 'upstream/main' into vector-64-128-256-C…
TIHan Feb 17, 2022
1d7e408
Merge branch 'vector-64-128-256-Create-to-get_Zero' into vec-zero-vn
TIHan Feb 17, 2022
0bdb08d
Merging
TIHan Feb 17, 2022
4bd81c7
Update assertionprop.cpp
TIHan Feb 18, 2022
396e8a1
Formatting
TIHan Feb 18, 2022
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use ResetHWIntrinsicId
  • Loading branch information
TIHan committed Jan 25, 2022
commit 1cf0b32a3fc779ada3b13ac4d521cce3c7eb0faa
28 changes: 25 additions & 3 deletions src/coreclr/jit/morph.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -13422,12 +13422,13 @@ GenTree* Compiler::fgOptimizeRelationalComparisonWithConst(GenTreeOp* cmp)
// node - HWIntrinsic node to examine
//
// Returns:
// The original node if no optimization happened.
// The original node if no optimization happened or if tree bashing occured.
// An alternative tree if an optimization happened.
//
// Notes:
// Checks for HWIntrinsic nodes: Vector64.Create/Vector128.Create/Vector256.Create,
// and if the call is one of these, attempt to optimize.
// This is post-order, meaning that it will not morph the children.
//
GenTree* Compiler::fgOptimizeHWIntrinsic(GenTreeHWIntrinsic* node)
{
Expand Down Expand Up @@ -13457,8 +13458,29 @@ GenTree* Compiler::fgOptimizeHWIntrinsic(GenTreeHWIntrinsic* node)

if (hwAllArgsAreConstZero)
{
return gtNewSimdZeroNode(node->gtType, node->GetSimdBaseJitType(), node->GetSimdSize(),
node->IsSimdAsHWIntrinsic());
switch (node->GetHWIntrinsicId())
{
case NI_Vector128_Create:
{
node->ResetHWIntrinsicId(NI_Vector128_get_Zero);
break;
}
#if defined(TARGET_XARCH)
case NI_Vector256_Create:
{
node->ResetHWIntrinsicId(NI_Vector256_get_Zero);
break;
}
#elif defined(TARGET_ARM64)
case NI_Vector64_Create:
{
node->ResetHWIntrinsicId(NI_Vector64_get_Zero);
break;
}
#endif
default:
unreached();
}
}
break;
}
Expand Down