Cleanup

src/coreclr/jit/codegenlinear.cpp

@@ -1657,7 +1657,7 @@ void CodeGen::genConsumeRegs(GenTree* tree)
 #ifdef FEATURE_SIMD
             // (In)Equality operation that produces bool result, when compared
             // against Vector zero, marks its Vector Zero operand as contained.
-            assert(tree->OperIsLeaf() || tree->IsSIMDZero() || tree->IsIntegralConstVector(0));
+            assert(tree->OperIsLeaf() || tree->IsSIMDZero());
 #else
             assert(tree->OperIsLeaf());
 #endif

src/coreclr/jit/gentree.cpp

@@ -17859,6 +17859,7 @@ bool GenTree::isContainableHWIntrinsic() const
 #elif TARGET_ARM64
     switch (AsHWIntrinsic()->GetHWIntrinsicId())
     {
+        case NI_Vector64_get_Zero:
         case NI_Vector128_get_Zero:
         {
             return true;

src/coreclr/jit/gentree.h

@@ -7712,6 +7712,23 @@ inline bool GenTree::IsSIMDZero() const
     }
 #endif
 
+#ifdef FEATURE_HW_INTRINSICS
+    if (gtOper == GT_HWINTRINSIC)
+    {
+        const GenTreeHWIntrinsic* node = AsHWIntrinsic();
+
+        if (node->GetOperandCount() == 0)
+        {
+            const var_types simdBaseType = node->GetSimdBaseType();
+            if (varTypeIsIntegral(simdBaseType) || varTypeIsFloating(simdBaseType))
+            {
+                const NamedIntrinsic intrinsicId = node->GetHWIntrinsicId();
+                return (intrinsicId == NI_Vector64_get_Zero) || (intrinsicId == NI_Vector128_get_Zero);
+            }
+        }
+    }
+#endif // FEATURE_HW_INTRINSICS
+
     return false;
 }
 

src/coreclr/jit/hwintrinsiccodegenarm64.cpp

@@ -377,9 +377,11 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
                     }
                     else
                     {
-                        if (intrin.id == NI_AdvSimd_CompareEqual && intrin.op2->isContained() &&
-                            intrin.op2->IsIntegralConstVector(0))
+                        if (intrin.op2->isContained())
                         {
+                            assert(HWIntrinsicInfo::SupportsContainment(intrin.id));
+                            assert(intrin.op2->IsSIMDZero());
+
                             GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op1Reg, opt);
                         }
                         else

src/coreclr/jit/instrsarm64.h

@@ -312,8 +312,8 @@ INST4(neg,         "neg",          0,      IF_EN4G,   0x4B0003E0,  0x4B0003E0,
 INST4(cmeq,        "cmeq",         0,      IF_EN4H,   0x7EE08C00,  0x2E208C00,  0x5E209800,  0x0E209800)
                                    //  cmeq    Vd,Vn,Vm             DV_3E  01111110111mmmmm 100011nnnnnddddd   7EE0 8C00   Vd,Vn,Vm   (scalar)
                                    //  cmeq    Vd,Vn,Vm             DV_3A  0Q101110XX1mmmmm 100011nnnnnddddd   2E20 8C00   Vd,Vn,Vm   (vector)
-                                   //  cmeq    Vd,Vn                DV_2L  01011110XX100000 100110nnnnnddddd   5E20 9800   Vd,Vn      (scalar)
-                                   //  cmeq    Vd,Vn                DV_2M  0Q001110XX100000 100110nnnnnddddd   0E20 9800   Vd,Vn      (vector)
+                                   //  cmeq    Vd,Vn                DV_2L  01011110XX100000 100110nnnnnddddd   5E20 9800   Vd,Vn,#0   (scalar - with zero)
+                                   //  cmeq    Vd,Vn                DV_2M  0Q001110XX100000 100110nnnnnddddd   0E20 9800   Vd,Vn,#0   (vector - with zero)
 
 INST4(cmge,        "cmge",         0,      IF_EN4H,   0x5EE03C00,  0x0E203C00,  0x7E208800,  0x2E208800)
                                    //  cmge    Vd,Vn,Vm             DV_3E  01011110111mmmmm 001111nnnnnddddd   5EE0 3C00   Vd,Vn,Vm   (scalar)

src/coreclr/jit/lowerarmarch.cpp

@@ -1871,7 +1871,7 @@ void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node)
 
             case NI_AdvSimd_CompareEqual:
             {
-                if (intrin.op2->IsIntegralConstVector(0))
+                if (intrin.op2->IsSIMDZero())
                 {
                     MakeSrcContained(node, intrin.op2);
                 }

src/coreclr/jit/lsraarm64.cpp

@@ -1101,10 +1101,14 @@ int LinearScan::BuildHWIntrinsic(GenTreeHWIntrinsic* intrinsicTree)
             }
         }
     }
-    else
+    else if (intrin.op2 != nullptr)
     {
-        if (intrin.op2 != nullptr &&
-            !(intrin.id == NI_AdvSimd_CompareEqual && intrin.op2->IsIntegralConstVector(0) && intrin.op2->isContained()))
+        if (intrin.op2->isContained())
+        {
+            assert(HWIntrinsicInfo::SupportsContainment(intrin.id));
+            assert(intrin.op2->IsSIMDZero());
+        }
+        else
         {
             // RMW intrinsic operands doesn't have to be delayFree when they can be assigned the same register as op1Reg
             // (i.e. a register that corresponds to read-modify-write operand) and one of them is the last use.