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JIT: Faster vector == Vector128.Zero on arm64 #65632

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Merged
EgorBo merged 11 commits into from
Feb 23, 2022
Merged

JIT: Faster vector == Vector128.Zero on arm64 #65632

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466afe6
Optimize vec == Vector.Zero for arm64
EgorBo Feb 20, 2022
3139218
Clean up
EgorBo Feb 20, 2022
a4143c4
Update lowerarmarch.cpp
EgorBo Feb 20, 2022
f9d45e0
Update lowerarmarch.cpp
EgorBo Feb 20, 2022
51f727f
Update lowerarmarch.cpp
EgorBo Feb 20, 2022
70e18b7
Apply Zoltan's patch
EgorBo Feb 21, 2022
1550865
Merge branch 'main' of https://github.com/dotnet/runtime into arm-fas…
EgorBo Feb 21, 2022
c1c7831
Address feedback
EgorBo Feb 21, 2022
5c1a77e
Merge branch 'main' of https://github.com/dotnet/runtime into arm-fas…
EgorBo Feb 22, 2022
59609c4
Address feedback
EgorBo Feb 22, 2022
bc9220b
use UINT for V128
EgorBo Feb 22, 2022
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use UINT for V128
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@EgorBo
EgorBo committed Feb 22, 2022
commit bc9220b69c403a5b6eccb3aa6cbc8d993745a92b
6 changes: 3 additions & 3 deletions src/coreclr/jit/lowerarmarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -891,9 +891,9 @@ void Lowering::LowerHWIntrinsicCmpOp(GenTreeHWIntrinsic* node, genTreeOps cmpOp)

if (!varTypeIsFloating(simdBaseType) && (op != nullptr))
{
// Use USHORT variant as it has better latency/throughput on some CPUs than UBYTE
GenTree* cmp =
comp->gtNewSimdHWIntrinsicNode(simdType, op, NI_AdvSimd_Arm64_MaxAcross, CORINFO_TYPE_USHORT, simdSize);
// Use USHORT for V64 and UINT for V128 due to better latency/TP on some CPUs
CorInfoType maxType = (simdSize == 8) ? CORINFO_TYPE_USHORT : CORINFO_TYPE_UINT;
GenTree* cmp = comp->gtNewSimdHWIntrinsicNode(simdType, op, NI_AdvSimd_Arm64_MaxAcross, maxType, simdSize);
BlockRange().InsertBefore(node, cmp);
LowerNode(cmp);
BlockRange().Remove(opZero);
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