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Adding support for vector constants via GenTreeVecCon #68874

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Merged
tannergooding merged 17 commits into from
May 31, 2022
Merged

Adding support for vector constants via GenTreeVecCon #68874

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d30818a
Adding support for vector constants via GenTreeVecCon
tannergooding May 3, 2022
2b82d9a
Merge remote-tracking branch 'dotnet/main' into vector-cns
tannergooding May 20, 2022
adbd04b
Responding to PR feedback
tannergooding May 20, 2022
55e44d6
Merge remote-tracking branch 'dotnet/main' into vector-cns
tannergooding May 25, 2022
db39727
Support tracking the underlying simdBaseJitType for GenTreeVecCon
tannergooding May 25, 2022
c4b1882
Merge remote-tracking branch 'dotnet/main' into vector-cns
tannergooding May 25, 2022
5b7d3e4
Applying formatting patch
tannergooding May 25, 2022
afd0ca1
Merge remote-tracking branch 'dotnet/main' into vector-cns
tannergooding May 26, 2022
52a3b70
Merge remote-tracking branch 'dotnet/main' into vector-cns
tannergooding May 26, 2022
b440ee3
Handle the scenario where TYP_SIMD8 is retyped to TYP_LONG or TYP_DOUBLE
tannergooding May 27, 2022
768a6d0
Ensure GenTreeVecCon tracks the simdSize so that TYP_SIMD8 ABI retypi…
tannergooding May 27, 2022
9d302b4
Ensure the create call and not the cloned local is lowered
tannergooding May 30, 2022
e2d7a2a
Merge remote-tracking branch 'dotnet/main' into vector-cns
tannergooding May 30, 2022
e35e385
Merge remote-tracking branch 'dotnet/main' into vector-cns
tannergooding May 31, 2022
3774181
Resolving PR feedback
tannergooding May 31, 2022
67ceb71
Ensure morph and rationalize check `OBJ(ADDR(CNS_VEC))`
tannergooding May 31, 2022
ac4dc2b
Update src/coreclr/jit/gentree.cpp
tannergooding May 31, 2022
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Applying formatting patch
  • Loading branch information
@tannergooding
tannergooding committed May 25, 2022
commit 5b7d3e4ef98efc12e4bbb0435874ee0a54da71a9
11 changes: 6 additions & 5 deletions src/coreclr/jit/gentree.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7018,7 +7018,8 @@ GenTree* Compiler::gtNewZeroConNode(var_types type, CorInfoType simdBaseJitType)

GenTreeVecCon* vecCon = gtNewVconNode(type, simdBaseJitType);
vecCon->gtSimd32Val = {};
return vecCon;;
return vecCon;
;
}

GenTree* Compiler::gtNewOneConNode(var_types type)
Expand Down Expand Up @@ -21174,7 +21175,7 @@ GenTree* Compiler::gtNewSimdNarrowNode(var_types type,
// return Avx2.Permute4x64(tmp4.AsUInt64(), SHUFFLE_WYZX).As<T>();

CorInfoType opBaseJitType = (simdBaseType == TYP_SHORT) ? CORINFO_TYPE_INT : CORINFO_TYPE_UINT;
CORINFO_CLASS_HANDLE clsHnd = gtGetStructHandleForSimdOrHW(type, opBaseJitType, isSimdAsHWIntrinsic);
CORINFO_CLASS_HANDLE clsHnd = gtGetStructHandleForSimdOrHW(type, opBaseJitType, isSimdAsHWIntrinsic);

tmp1 = gtNewSimdHWIntrinsicNode(type, gtNewIconNode(0x0000FFFF), NI_Vector256_Create, opBaseJitType,
simdSize, isSimdAsHWIntrinsic);
Expand Down Expand Up @@ -21214,7 +21215,7 @@ GenTree* Compiler::gtNewSimdNarrowNode(var_types type,
// return Avx2.Permute4x64(tmp3.AsUInt64(), SHUFFLE_WYZX).AsUInt32();

CorInfoType opBaseJitType = (simdBaseType == TYP_INT) ? CORINFO_TYPE_LONG : CORINFO_TYPE_ULONG;
CORINFO_CLASS_HANDLE clsHnd = gtGetStructHandleForSimdOrHW(type, opBaseJitType, isSimdAsHWIntrinsic);
CORINFO_CLASS_HANDLE clsHnd = gtGetStructHandleForSimdOrHW(type, opBaseJitType, isSimdAsHWIntrinsic);

GenTree* op1Dup;
op1 = impCloneExpr(op1, &op1Dup, clsHnd, (unsigned)CHECK_SPILL_ALL,
Expand Down Expand Up @@ -21312,7 +21313,7 @@ GenTree* Compiler::gtNewSimdNarrowNode(var_types type,
// ...

CorInfoType opBaseJitType = (simdBaseType == TYP_SHORT) ? CORINFO_TYPE_INT : CORINFO_TYPE_UINT;
CORINFO_CLASS_HANDLE clsHnd = gtGetStructHandleForSimdOrHW(type, opBaseJitType, isSimdAsHWIntrinsic);
CORINFO_CLASS_HANDLE clsHnd = gtGetStructHandleForSimdOrHW(type, opBaseJitType, isSimdAsHWIntrinsic);

if (compOpportunisticallyDependsOn(InstructionSet_SSE41))
{
Expand Down Expand Up @@ -21406,7 +21407,7 @@ GenTree* Compiler::gtNewSimdNarrowNode(var_types type,
// return Sse2.UnpackLow(tmp1, tmp2).As<T>();

CorInfoType opBaseJitType = (simdBaseType == TYP_INT) ? CORINFO_TYPE_LONG : CORINFO_TYPE_ULONG;
CORINFO_CLASS_HANDLE clsHnd = gtGetStructHandleForSimdOrHW(type, opBaseJitType, isSimdAsHWIntrinsic);
CORINFO_CLASS_HANDLE clsHnd = gtGetStructHandleForSimdOrHW(type, opBaseJitType, isSimdAsHWIntrinsic);

GenTree* op1Dup;
op1 = impCloneExpr(op1, &op1Dup, clsHnd, (unsigned)CHECK_SPILL_ALL,
Expand Down
5 changes: 2 additions & 3 deletions src/coreclr/jit/gentree.h
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Original file line number Diff line number Diff line change
Expand Up @@ -3288,7 +3288,7 @@ struct GenTreeVecCon : public GenTree
};

private:
unsigned char gtSimdBaseJitType; // SIMD vector base JIT type
unsigned char gtSimdBaseJitType; // SIMD vector base JIT type

public:
CorInfoType GetSimdBaseJitType() const
Expand Down Expand Up @@ -3430,8 +3430,7 @@ struct GenTreeVecCon : public GenTree
}

GenTreeVecCon(var_types type, CorInfoType simdBaseJitType)
: GenTree(GT_CNS_VEC, type)
, gtSimdBaseJitType((unsigned char)simdBaseJitType)
: GenTree(GT_CNS_VEC, type), gtSimdBaseJitType((unsigned char)simdBaseJitType)
{
assert(varTypeIsSIMD(type));
assert(gtSimdBaseJitType == simdBaseJitType);
Expand Down