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Ensure that the SSE fallback for Vector3.Dot masks off the unused element of op1 and op2 #74932

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Merged
tannergooding merged 3 commits into from
Sep 2, 2022
Merged

Ensure that the SSE fallback for Vector3.Dot masks off the unused element of op1 and op2 #74932

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5b49a4d
Ensure that the SSE fallback for Vector3.Dot masks off the unused ele…
tannergooding Sep 1, 2022
b19aec7
Applying formatting patch
tannergooding Sep 1, 2022
2945d9c
Ensure we use TYP_SIMD16 in for the simdType when generating the fall…
tannergooding Sep 1, 2022
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Ensure we use TYP_SIMD16 in for the simdType when generating the fall… 
…back Dot nodes
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@tannergooding
tannergooding committed Sep 1, 2022
commit 2945d9c3827f671b729d461ab0e8fdc987976d11
16 changes: 10 additions & 6 deletions src/coreclr/jit/lowerxarch.cpp
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Expand Up @@ -3423,11 +3423,15 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node)
// from including it in the computed result. We need to do this for both op1 and
// op2 in case one of them is `NaN` (because Zero * NaN == NaN)

simd12_t simd12Val = {};
simd16_t simd16Val = {};

simd12Val.i32[0] = -1;
simd12Val.i32[1] = -1;
simd12Val.i32[2] = -1;
simd16Val.i32[0] = -1;
simd16Val.i32[1] = -1;
simd16Val.i32[2] = -1;
simd16Val.i32[3] = +0;

simdType = TYP_SIMD16;
simdSize = 16;

// We will be constructing the following parts:
// ...
Expand All @@ -3448,7 +3452,7 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node)
// ...

GenTreeVecCon* vecCon1 = comp->gtNewVconNode(simdType, simdBaseJitType);
vecCon1->gtSimd12Val = simd12Val;
vecCon1->gtSimd16Val = simd16Val;

BlockRange().InsertAfter(op1, vecCon1);

Expand Down Expand Up @@ -3477,7 +3481,7 @@ GenTree* Lowering::LowerHWIntrinsicDot(GenTreeHWIntrinsic* node)
// ...

GenTreeVecCon* vecCon2 = comp->gtNewVconNode(simdType, simdBaseJitType);
vecCon2->gtSimd12Val = simd12Val;
vecCon2->gtSimd16Val = simd16Val;

BlockRange().InsertAfter(op2, vecCon2);

Expand Down