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@clamp03 clamp03 commented Feb 17, 2023

Based on LOONGARCH64, implemented RISC-V.

What I checked are

  • Successfully cross-build for RISC-V.
  • Run A simple application "helloworld"
  • Fail a test in clr.paltest

There are much work to be done. I hope to work together on upstream repo.
Thank you.

Related Issue: #36748

Fix a bug in a stub.
Update unimplemented functions
Fix in emitInsMayWriteToGCReg
Update unimplemented functions
Fix bugs
Set JitFramed to True to avoid assert in jit/lclvars.cpp.
Implement unimplemented function in codegenriscv64
Now HelloWorld runs with CHECKED build.
Reduce FixupPrecode size to fix a crash.
Fix a crash in Release mode. Instruction generation is in DEBUG macro.
Fixed after upstream rebase
Fix tests build fails
Update RISCV R_R_R instructions
- threading/NamedMutex/test1/paltest_namedmutex_test1
  disabled NAMED_MUTEX_USE_PTHREAD_MUTEX
- threading/YieldProcessor/test1/paltest_yieldprocessor_test1
  wfi is executed in privileged mode.
  add a fence instruction like loongarch
Update Conditions/Conditional branches
@ghost ghost added community-contribution Indicates that the PR has been added by a community member area-VM-coreclr labels Feb 17, 2023
@clamp03
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clamp03 commented Feb 17, 2023

@jkotas, There are many errors and unimplemented codes. Please review and let me know what you think. Thank you so much.
@wscho77 @HJLeee @JongHeonChoi @alpencolt @gbalykov

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am11 commented Feb 17, 2023

Great progress! 👍

@clamp03 fwiw, the initial patch was #73385, yours is much advanced progress! ;)

The tracking issue for CoreCLR is #75749.

You may want to split src/coreclr/pal, src/coreclr/vm, src/coreclr/jit etc. into separate PRs as they will be reviewed by different teams.

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jkotas commented Feb 17, 2023

@clamp03 Thank for working on RISC-V port! Would you mind sharing your motivation for this port? Is there a specific scenario that you are targeting?

You may want to split src/coreclr/pal, src/coreclr/vm, src/coreclr/jit etc. into separate PRs as they will be reviewed by different teams.

+1 This will need to be split into multiple PRs to make the review manageable.

cc @dotnet/jit-contrib @jeffschwMSFT

@clamp03
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clamp03 commented Feb 18, 2023

@am11 @jkotas Thank you for the review.
I will tidy up codes and split into separate PRs.

We want to run Tizen on risc-v. Many opensource modules except .net runtime are already ported to risc-v. We don't have enough time and resources. We need helps from you and others. Thank you.

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richlander commented Feb 18, 2023

Our general policy on ports is covered in this recent post: https://devblogs.microsoft.com/dotnet/why-dotnet/#binary-distributions

Glad to see the interest in the combination of .NET and RISC-V.

LEAF_ENTRY RtlRestoreContext, _TEXT
#ifdef HAS_ASAN
lw t1, CONTEXT_ContextFlags(a0)
andi t1, t1, 0x1 << CONTEXT_FLOATING_POINT_BIT
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In arm64 implementation in a similar place CONTEXT_CONTROL_BIT is used instead of CONTEXT_FLOATING_POINT_BIT. Isn't this a bug in loongarch64 implementation?

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This time I think we don't need ASAN support for RISC-V.
I removed those and left a TODO comment.

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clamp03 commented Feb 20, 2023

I pushed four PRs. Thank you!
#82379
#82380
#82381
#82382

@clamp03 clamp03 closed this Feb 20, 2023
@ghost ghost locked as resolved and limited conversation to collaborators Mar 22, 2023
@clamp03 clamp03 deleted the riscv64 branch April 28, 2023 04:09
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6 participants