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da21fa4
[WIP] RISCV64 REL BUILD
clamp03 Oct 26, 2022
9ff3bdc
[WIP] RISCV64 DBG BUILD
clamp03 Nov 8, 2022
499e598
[WIP] FIX
clamp03 Nov 8, 2022
7433745
[WIP] FIX WHAT I DID FOR THREAD STORE TEST
clamp03 Nov 10, 2022
7587b73
[WIP] UPDATE ASSEMBLY FUNCTIONS and ADD CRASH TO UNIMPLEMENTED
clamp03 Nov 10, 2022
c7bd561
[WIP] UPDATE CRTHELPERS
clamp03 Nov 10, 2022
4ca0934
[WIP] UPDATE EXCEPTIONHANDLER AND CALLDESCRWORKERRISCV64
clamp03 Nov 10, 2022
8bdde90
[WIP] UPDATE ACTIVATIONHANDLERWRAPPER
clamp03 Nov 10, 2022
260fdc4
[WIP] CALLSIGNALHANDLEWRAPPER
clamp03 Nov 10, 2022
de1c03e
[WIP] FLOATCONVERSION, DBGHELPERS
clamp03 Nov 10, 2022
1a45b75
[WIP] PAL, ASMCONSTANTS, CONTEXT2
clamp03 Nov 11, 2022
da10fc8
[WIP] REMOVE ACTIVATIONHANDLERWRAPPER, DISPATCHEXCEPTIONWRAPPER
clamp03 Nov 11, 2022
0cb6eb6
[WIP] ADD CRASH INSTRS FOR UNINPLEMENTED
clamp03 Nov 11, 2022
896a978
[WIP] ASMHELPERS
clamp03 Nov 14, 2022
7c9508c
[WIP] PINVOKESTUBS
clamp03 Nov 14, 2022
f6e85fa
[WIP] RESTORE getcontext.S and setcontext.S in libunwind
clamp03 Nov 14, 2022
4c12c26
[WIP] FIX THREADS.CPP
clamp03 Nov 15, 2022
f5e184d
[WIP] FIX PRECODE
clamp03 Nov 15, 2022
df30a97
[WIP] SET REG
clamp03 Nov 15, 2022
322c2b9
[WIP] FIX INTERPRETER
clamp03 Nov 21, 2022
1120e51
[WIP] Revert Interpreter Code Changes
clamp03 Nov 24, 2022
93d30e7
[WIP] JIT
clamp03 Nov 24, 2022
47938e6
[WIP] JIT
clamp03 Nov 25, 2022
a01b735
[WIP] JIT
clamp03 Nov 30, 2022
7bf58ed
[WIP] JIT
clamp03 Dec 1, 2022
da5220a
[WIP] JIT
clamp03 Dec 2, 2022
c7063e9
[WIP] JIT
clamp03 Dec 5, 2022
55a83da
[WIP] JIT
clamp03 Dec 5, 2022
894ac25
[WIP] JIT
clamp03 Dec 6, 2022
a5d54c3
[WIP] JIT
clamp03 Dec 7, 2022
6377887
[WIP] JIT
clamp03 Dec 9, 2022
95119c7
[WIP] JIT
clamp03 Dec 19, 2022
eb939c1
[WIP] JIT
clamp03 Dec 20, 2022
c241e32
[WIP] JIT
clamp03 Dec 20, 2022
0893b92
[WIP] JIT
clamp03 Dec 20, 2022
a03513a
[WIP] JIT
clamp03 Dec 21, 2022
e714c1a
[WIP] JIT
clamp03 Dec 22, 2022
dfde411
[WIP] JIT
clamp03 Dec 22, 2022
3683323
[WIP] JIT
clamp03 Dec 23, 2022
733a4d5
[WIP] JIT
clamp03 Dec 26, 2022
18c37ce
[WIP] JIT
clamp03 Dec 27, 2022
ade1a59
[WIP] JIT
clamp03 Dec 29, 2022
b3cf2ae
[WIP] JIT
clamp03 Dec 29, 2022
589f6a3
[WIP] JIT
clamp03 Jan 2, 2023
8f91e27
[WIP] JIT
clamp03 Jan 2, 2023
6882d87
[WIP] FIX JIT ERRORS
clamp03 Jan 3, 2023
ca1ad78
[WIP] FIX PROLOG REGISTER SAVES
clamp03 Jan 3, 2023
29699c1
[WIP] FIX and UPDATE JIT
clamp03 Jan 3, 2023
54f892b
[WIP] IMPLEMENTS SHIFT, ROTATE, NEG, NOT and FENCE
clamp03 Jan 3, 2023
558f214
[WIP] JIT UPDATE
clamp03 Jan 4, 2023
bc14f0a
[WIP] FIX DISP
clamp03 Jan 5, 2023
d8fe5ca
[WIP] JIT DEBUGGING
clamp03 Jan 5, 2023
4bc1b27
[WIP] JIT
clamp03 Jan 9, 2023
e1da0a6
[WIP] JIT
clamp03 Jan 10, 2023
b5f8bd5
[WIP] JIT
clamp03 Jan 11, 2023
f23ef1b
[WIP] JIT
clamp03 Jan 11, 2023
3fbfff1
[WIP] FIX JIT
clamp03 Jan 12, 2023
6b64b3d
[WIP] JIT
clamp03 Jan 12, 2023
52aafd2
[WIP] JIT
clamp03 Jan 12, 2023
eea327c
[WIP] JIT
clamp03 Jan 13, 2023
81fe2a0
[WIP] JIT
clamp03 Jan 13, 2023
13650ae
[WIP] JIT
clamp03 Jan 13, 2023
e753f43
[WIP] JIT
clamp03 Jan 16, 2023
d44f9ec
[WIP] JIT
clamp03 Jan 16, 2023
a601385
[WIP] JIT
clamp03 Jan 17, 2023
12ccf4f
[WIP] JIT
clamp03 Jan 17, 2023
8a87d86
[WIP] JIT
clamp03 Jan 18, 2023
c00a4cd
[WIP] JIT
clamp03 Jan 18, 2023
57df5a9
[WIP] JIT
clamp03 Jan 19, 2023
0db2c5c
[WIP] JIT
clamp03 Jan 19, 2023
be097ae
[WIP] JIT
clamp03 Jan 19, 2023
5f2eb7b
[WIP] JIT
clamp03 Jan 20, 2023
e9b852e
[WIP] JIT
clamp03 Jan 20, 2023
4709724
[WIP] JIT
clamp03 Jan 20, 2023
c58aee1
[WIP] JIT
clamp03 Jan 20, 2023
498276f
[WIP] JIT
clamp03 Jan 20, 2023
5cae87a
[WIP] JIT
clamp03 Jan 30, 2023
af66496
[WIP] JIT
clamp03 Jan 31, 2023
a6791ed
[WIP] JIT
clamp03 Feb 1, 2023
15b448e
[WIP] JIT
clamp03 Feb 1, 2023
407e25d
[WIP] JIT
clamp03 Feb 1, 2023
2b3b528
[WIP] JIT
clamp03 Feb 2, 2023
5638069
[WIP] JIT
clamp03 Feb 2, 2023
9641baf
[WIP] JIT
clamp03 Feb 3, 2023
5070785
[WIP] JIT
clamp03 Feb 3, 2023
553c1fd
[WIP] JIT
clamp03 Feb 7, 2023
e7a0474
[WIP] TESTS
clamp03 Feb 13, 2023
e147059
[WIP] JIT
clamp03 Feb 13, 2023
91ce589
[WIP] PALTEST
clamp03 Feb 15, 2023
0827ede
[WIP] FIX AFTER REBASE
clamp03 Feb 17, 2023
6b81f2d
[WIP] Remove commented codes
clamp03 Feb 17, 2023
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[WIP] Revert Interpreter Code Changes
  • Loading branch information
clamp03 committed Feb 17, 2023
commit 1120e5181625b1562f79e1ed8fd947c8ebdbcafa
41 changes: 1 addition & 40 deletions src/coreclr/vm/interpreter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1635,46 +1635,7 @@ CorJitResult Interpreter::GenerateInterpreterStub(CEEInfo* comp,
#elif defined(HOST_LOONGARCH64)
assert(!"unimplemented on LOONGARCH yet");
#elif defined(HOST_RISCV64)
UINT stackFrameSize = argState.numFPRegArgSlots;

sl.EmitProlog(argState.numRegArgs, argState.numFPRegArgSlots, 0 /*cCalleeSavedRegs*/, 0);

#if INTERP_ILSTUBS
if (pMD->IsILStub())
{
// Third argument(x12) is stubcontext, in x7 (METHODDESC_REGISTER)
sl.EmitMovReg(IntReg(12), IntReg(7));
}
else
#endif
{
// For a non-ILStub method, push NULL as the third stubContext argument
sl.EmitMovConstant(IntReg(12), 0);
}

// Second arg is pointer to the basei of the ILArgs -- i.e., the current stack value
// sl.EmitAddImm(IntReg(1), RegSp, sl.GetSavedRegArgsOffset());

// First arg is the pointer to the interpMethodInfo structure
#if INTERP_ILSTUBS
if (!pMD->IsILStub())
#endif
{
// interpMethodInfo is already in x8, so copy it from x8
sl.EmitMovReg(IntReg(10), IntReg(8)); // TODO what is x8???
}
#if INTERP_ILSTUBS
else
{
// We didn't do the short-circuiting, therefore interpMethInfo is
// not stored in a register (x8) before. so do it now.
sl.EmitMovConstant(IntReg(10), reinterpret_cast<UINT64>(interpMethInfo));
}
#endif

sl.EmitCallLabel(sl.NewExternalCodeLabel((LPVOID)interpretMethodFunc), FALSE, FALSE);

sl.EmitEpilog();
assert(!"unimplemented on RISCV64 yet");
#else
#error unsupported platform
#endif
Expand Down
9 changes: 0 additions & 9 deletions src/coreclr/vm/riscv64/cgencpu.h
Original file line number Diff line number Diff line change
Expand Up @@ -377,16 +377,7 @@ class StubLinkerCPU : public StubLinker
void EmitLoadRegReg(IntReg Xt, IntReg Xn, IntReg Xm, DWORD option);

void EmitCallRegister(IntReg reg);
void EmitProlog(unsigned short cIntRegArgs,
unsigned short cFloatRegArgs,
unsigned short cCalleeSavedRegs,
unsigned short cbStackSpace = 0);

void EmitEpilog();

void EmitRet(IntReg reg);


};
#endif

Expand Down
109 changes: 0 additions & 109 deletions src/coreclr/vm/riscv64/stubs.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -479,115 +479,6 @@ void StubLinkerCPU::EmitJumpRegister(IntReg regTarget)
_ASSERTE(!"RISCV64: not implementation on riscv64!!!");
}

void StubLinkerCPU::EmitProlog(unsigned short cIntRegArgs, unsigned short cFloatRegArgs, unsigned short cCalleeSavedRegs, unsigned short cbStackSpace)
{
_ASSERTE(!m_fProlog);

unsigned short numberOfEntriesOnStack = 2 + cIntRegArgs + cFloatRegArgs + cCalleeSavedRegs; // 2 for fp, ra

// Stack needs to be 16 byte (2 qword) aligned. Compute the required padding before saving it
unsigned short totalPaddedFrameSize = static_cast<unsigned short>(ALIGN_UP(cbStackSpace + numberOfEntriesOnStack *sizeof(void*), 2 * sizeof(void*)));
// The padding is going to be applied to the local stack
cbStackSpace = totalPaddedFrameSize - numberOfEntriesOnStack * sizeof(void*);

// Record the parameters of this prolog so that we can generate a matching epilog and unwind info.
DescribeProlog(cIntRegArgs, cFloatRegArgs, cCalleeSavedRegs, cbStackSpace);


// N.B Despite the range of a jump with a sub sp is 4KB, we're limiting to 504 to save from emitting right prolog that's
// expressable in unwind codes efficiently. The largest offset in typical unwindinfo encodings that we use is 504.
// so allocations larger than 504 bytes would require setting the SP in multiple strides, which would complicate both
// prolog and epilog generation as well as unwindinfo generation.
_ASSERTE((totalPaddedFrameSize <= 504) && "NYI:RISCV64 Implement StubLinker prologs with larger than 504 bytes of frame size");
if (totalPaddedFrameSize > 504)
COMPlusThrow(kNotSupportedException);

// Regarding the order of operations in the prolog and epilog;
// If the prolog and the epilog matches each other we can simplify emitting the unwind codes and save a few
// bytes of unwind codes by making prolog and epilog share the same unwind codes.
// In order to do that we need to make the epilog be the reverse of the prolog.
// But we wouldn't want to add restoring of the argument registers as that's completely unnecessary.
// Besides, saving argument registers cannot be expressed by the unwind code encodings.
// So, we'll push saving the argument registers to the very last in the prolog, skip restoring it in epilog,
// and also skip reporting it to the OS.
//
// Another bit that we can save is resetting the frame pointer.
// This is not necessary when the SP doesn't get modified beyond prolog and epilog. (i.e no alloca/localloc)
// And in that case we don't need to report setting up the FP either.


// 1. Relocate SP
EmitSubImm(RegSp, RegSp, totalPaddedFrameSize);

unsigned cbOffset = 2 * sizeof(void*) + cbStackSpace; // 2 is for fp, ra

// 2. Store callee-saved registers
#if 0
_ASSERTE(cCalleeSavedRegs <= 13);
if (cCalleeSavedRegs != 0)
{
EmitLoadStoreRegPairImm(eSTORE, IntReg(3), IntReg(4), RegSp, cbOffset);
EmitLoadStoreRegPairImm(eSTORE, IntReg(9), IntReg(18), RegSp, cbOffset + 2 * sizeof(void*));
EmitLoadStoreRegPairImm(eSTORE, IntReg(19), IntReg(20), RegSp, cbOffset + 4 * sizeof(void*));
EmitLoadStoreRegPairImm(eSTORE, IntReg(21), IntReg(22), RegSp, cbOffset + 6 * sizeof(void*));
EmitLoadStoreRegPairImm(eSTORE, IntReg(23), IntReg(24), RegSp, cbOffset + 8 * sizeof(void*));
EmitLoadStoreRegPairImm(eSTORE, IntReg(25), IntReg(26), RegSp, cbOffset + 10 * sizeof(void*));
EmitLoadStoreRegImm(eSTORE, IntReg(27), RegSp, cbOffset + 12 * sizeof(void*));
}
#endif

// 3. Store FP/RA
EmitLoadStoreRegPairImm(eSTORE, RegFp, RegRa, RegSp, cbStackSpace);

// 4. Set the frame pointer
EmitMovReg(RegFp, RegSp);

// 5. Store floating point argument registers
cbOffset += cCalleeSavedRegs * sizeof(void*);
_ASSERTE(cFloatRegArgs <= 8);
for (unsigned short i = 0; i < (cFloatRegArgs / 2) * 2; i += 2)
EmitLoadStoreRegPairImm(eSTORE, FloatReg(i + 10), FloatReg(i + 11), RegSp, cbOffset + i * sizeof(void*));
if ((cFloatRegArgs % 2) == 1)
EmitLoadStoreRegImm(eSTORE, FloatReg(cFloatRegArgs - 1 + 10), RegSp, cbOffset + (cFloatRegArgs - 1) * sizeof(void*));

// 6. Store int argument registers
cbOffset += cFloatRegArgs * sizeof(void*);
_ASSERTE(cIntRegArgs <= 8);
for (unsigned short i = 0 ; i < (cIntRegArgs / 2) * 2; i += 2)
EmitLoadStoreRegPairImm(eSTORE, IntReg(i + 10), IntReg(i + 11), RegSp, cbOffset + i * sizeof(void*));
if ((cIntRegArgs % 2) == 1)
EmitLoadStoreRegImm(eSTORE,IntReg(cIntRegArgs-1 + 10), RegSp, cbOffset + (cIntRegArgs - 1) * sizeof(void*));
}

void StubLinkerCPU::EmitEpilog()
{
_ASSERTE(m_fProlog);

// 6. Restore int argument registers
// nop: We don't need to. They are scratch registers

// 5. Restore floating point argument registers
// nop: We don't need to. They are scratch registers

// 4. Restore the SP from FP
// N.B. We're assuming that the stublinker stubs doesn't do alloca, hence nop

// 3. Restore FP/RA
EmitLoadStoreRegPairImm(eLOAD, RegFp, RegRa, RegSp, m_cbStackSpace);

// 2. restore the calleeSavedRegisters
unsigned cbOffset = 2*sizeof(void*) + m_cbStackSpace; // 2 is for fp,lr
if ((m_cCalleeSavedRegs % 2) ==1)
EmitLoadStoreRegImm(eLOAD, IntReg(m_cCalleeSavedRegs - 1), RegSp, cbOffset + (m_cCalleeSavedRegs - 1) * sizeof(void*));
for (int i = (m_cCalleeSavedRegs / 2) * 2 - 2; i >= 0; i -= 2)
EmitLoadStoreRegPairImm(eLOAD, IntReg(19 + i), IntReg(19 + i + 1), RegSp, cbOffset + i * sizeof(void*));

// 1. Restore SP
EmitAddImm(RegSp, RegSp, GetStackFrameSize());
EmitRet(RegRa);
;
}

void StubLinkerCPU::EmitRet(IntReg Xn)
{
Emit32((DWORD)(0x00000067 | (Xn << 15))); // jalr X0, 0(Xn)
Expand Down
33 changes: 1 addition & 32 deletions src/coreclr/vm/stublink.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -377,13 +377,6 @@ StubLinker::StubLinker()
m_cbStackSpace = 0;
#endif
#endif // STUBLINKER_GENERATES_UNWIND_INFO
#ifdef TARGET_RISCV64
m_fProlog = FALSE;
m_cIntRegArgs = 0;
m_cFloatRegArgs = 0;
m_cCalleeSavedRegs = 0;
m_cbStackSpace = 0;
#endif
}


Expand Down Expand Up @@ -1898,31 +1891,7 @@ UINT StubLinker::GetStackFrameSize()
return m_cbStackSpace + (2 + m_cCalleeSavedRegs + m_cIntRegArgs + m_cVecRegArgs)*sizeof(void*);
}

#elif defined(TARGET_RISCV64)
void StubLinker::DescribeProlog(UINT cIntRegArgs, UINT cFloatRegArgs, UINT cCalleeSavedRegs, UINT cbStackSpace)
{
m_fProlog = TRUE;
m_cIntRegArgs = cIntRegArgs;
m_cFloatRegArgs = cFloatRegArgs;
m_cCalleeSavedRegs = cCalleeSavedRegs;
m_cbStackSpace = cbStackSpace;
}

UINT StubLinker::GetSavedRegArgsOffset()
{
_ASSERTE(m_fProlog);
// This is the offset from SP
// We're assuming that the stublinker will push the arg registers to the bottom of the stack frame
return m_cbStackSpace + (2 + m_cCalleeSavedRegs)*sizeof(void*); // 2 is for FP and RA
}

UINT StubLinker::GetStackFrameSize()
{
_ASSERTE(m_fProlog);
return m_cbStackSpace + (2 + m_cCalleeSavedRegs + m_cIntRegArgs + m_cFloatRegArgs) * sizeof(void*);
}

#endif // ifdef TARGET_ARM, elif defined(TARGET_ARM64), elif defined(TARGET_RISCV64)
#endif // ifdef TARGET_ARM, elif defined(TARGET_ARM64)

#endif // #ifndef DACCESS_COMPILE

Expand Down
15 changes: 0 additions & 15 deletions src/coreclr/vm/stublink.h
Original file line number Diff line number Diff line change
Expand Up @@ -229,10 +229,6 @@ class StubLinker
void DescribeProlog(UINT cIntRegArgs, UINT cVecRegArgs, UINT cCalleeSavedRegs, UINT cbStackFrame);
UINT GetSavedRegArgsOffset();
UINT GetStackFrameSize();
#elif defined(TARGET_RISCV64)
void DescribeProlog(UINT cIntRegArgs, UINT cFloatRegArgs, UINT cCalleeSavedRegs, UINT cbStackFrame);
UINT GetSavedRegArgsOffset();
UINT GetStackFrameSize();
#endif

//===========================================================================
Expand Down Expand Up @@ -308,17 +304,6 @@ class StubLinker
UINT m_cbStackSpace; // Additional stack space for return buffer and stack alignment
#endif // TARGET_ARM64

#ifdef TARGET_RISCV64
protected:
BOOL m_fProlog; // True if DescribeProlog has been called
UINT m_cIntRegArgs; // Count of int register arguments (a0 - a7)
UINT m_cFloatRegArgs; // Count of FP register arguments (fa0 - fa7)
UINT m_cCalleeSavedRegs; // Count of callee saved registers (sp, gp, tp, s0 - s11)
UINT m_cbStackSpace; // Additional stack space for return buffer and stack alignment
#endif // TARGET_ARM64



#ifdef STUBLINKER_GENERATES_UNWIND_INFO

#ifdef _DEBUG
Expand Down