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fix for sharedlibrary
  • Loading branch information
kunalspathak committed Feb 6, 2024
commit 1bc76ce648584c11e290b620dfd1da87b7f7d3e6
17 changes: 9 additions & 8 deletions src/coreclr/jit/codegenarmarch.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3623,9 +3623,8 @@ void CodeGen::genCallInstruction(GenTreeCall* call)
//
assert(genIsValidIntReg(target->GetRegNum()));

bool isTlsHandleTarget = false;
#ifdef TARGET_ARM64
isTlsHandleTarget =
bool isTlsHandleTarget =
compiler->IsTargetAbi(CORINFO_NATIVEAOT_ABI) && TargetOS::IsUnix && target->IsTlsIconHandle();

if (isTlsHandleTarget)
Expand All @@ -3642,22 +3641,22 @@ void CodeGen::genCallInstruction(GenTreeCall* call)
// correct in the format the way linker needs. Also, we might end up spilling or
// reloading a register, which can break the pattern.
//
// adrp x0, :tlsdesc:tlsRoot ; R_AARCH64_TLSDESC_ADR_PAGE21
// add x0, x0, #0 ; R_AARCH64_TLSDESC_ADD_LO12
// mrs x1, tpidr_el0
// adrp x0, :tlsdesc:tlsRoot ; R_AARCH64_TLSDESC_ADR_PAGE21
// ldr x2, [x0] ; R_AARCH64_TLSDESC_LD64_LO12
// add x0, x0, #0 ; R_AARCH64_TLSDESC_ADD_LO12
// blr x2 ; R_AARCH64_TLSDESC_CALL
// add x0, x1, x0
// We guaranteed in LSRA that r0, r1 and r2 are assigned to this node.

// adrp/add
instGen_Set_Reg_To_Imm(attr, REG_R0, (ssize_t)methHnd,
INS_FLAGS_DONT_CARE DEBUGARG(iconNode->gtTargetHandle) DEBUGARG(iconNode->gtFlags));
// mrs
emitter->emitIns_R(INS_mrs_tpid0, attr, REG_R1);

// adrp
// ldr
emitter->emitIns_R_R_I(INS_ldr, attr, target->GetRegNum(), REG_R0, (ssize_t)methHnd);
// add
emitter->emitIns_Adrp_Ldr_Add(attr, REG_R0, target->GetRegNum(), (ssize_t)methHnd
DEBUGARG(iconNode->gtTargetHandle) DEBUGARG(iconNode->gtFlags));
}
#endif

Expand All @@ -3672,11 +3671,13 @@ void CodeGen::genCallInstruction(GenTreeCall* call)
target->GetRegNum(),
call->IsFastTailCall());

#ifdef TARGET_ARM64
if (isTlsHandleTarget)
{
// add x0, x1, x0
GetEmitter()->emitIns_R_R_R(INS_add, EA_8BYTE, REG_R0, REG_R1, REG_R0);
}
#endif
// clang-format on
}
else
Expand Down
60 changes: 52 additions & 8 deletions src/coreclr/jit/emitarm64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -13004,6 +13004,58 @@ void emitter::emitIns_R_AR(instruction ins, emitAttr attr, regNumber ireg, regNu
NYI("emitIns_R_AR");
}

// This computes address from the immediate which is relocatable.
void emitter::emitIns_Adrp_Ldr_Add(emitAttr attr,
regNumber ireg, regNumber reg2,
ssize_t addr DEBUGARG(size_t targetHandle) DEBUGARG(GenTreeFlags gtFlags))
{
assert(EA_IS_RELOC(attr));
assert(EA_IS_CNS_TLSGD_RELOC(attr));

emitAttr size = EA_SIZE(attr);
insFormat fmt = IF_DI_1E;
bool needAdd = false;
instrDescJmp* id = emitNewInstrJmp();

// adrp
id->idIns(INS_adrp);
id->idInsFmt(fmt);
id->idInsOpt(INS_OPTS_NONE);
id->idOpSize(size);
id->idAddr()->iiaAddr = (BYTE*)addr;
id->idReg1(ireg);
id->idSetIsDspReloc();
id->idSetTlsGD();

#ifdef DEBUG
id->idDebugOnlyInfo()->idMemCookie = targetHandle;
id->idDebugOnlyInfo()->idFlags = gtFlags;
#endif

dispIns(id);
appendToCurIG(id);

// ldr
emitIns_R_R_I(INS_ldr, attr, reg2, ireg, (ssize_t)addr);

// add
fmt = IF_DI_2A;
instrDesc* addId = emitNewInstr(attr);
assert(id->idIsReloc());

addId->idIns(INS_add);
addId->idInsFmt(fmt);
addId->idInsOpt(INS_OPTS_NONE);
addId->idOpSize(size);
addId->idAddr()->iiaAddr = (BYTE*)addr;
addId->idReg1(ireg);
addId->idReg2(ireg);
addId->idSetTlsGD();

dispIns(addId);
appendToCurIG(addId);
}

// This computes address from the immediate which is relocatable.
void emitter::emitIns_R_AI(instruction ins,
emitAttr attr,
Expand Down Expand Up @@ -13036,10 +13088,6 @@ void emitter::emitIns_R_AI(instruction ins,
id->idAddr()->iiaAddr = (BYTE*)addr;
id->idReg1(ireg);
id->idSetIsDspReloc();
if (EA_IS_CNS_TLSGD_RELOC(attr))
{
id->idSetTlsGD();
}
#ifdef DEBUG
id->idDebugOnlyInfo()->idMemCookie = targetHandle;
id->idDebugOnlyInfo()->idFlags = gtFlags;
Expand All @@ -13063,10 +13111,6 @@ void emitter::emitIns_R_AI(instruction ins,
id->idAddr()->iiaAddr = (BYTE*)addr;
id->idReg1(ireg);
id->idReg2(ireg);
if (EA_IS_CNS_TLSGD_RELOC(attr))
{
id->idSetTlsGD();
}

dispIns(id);
appendToCurIG(id);
Expand Down
4 changes: 4 additions & 0 deletions src/coreclr/jit/emitarm64.h
Original file line number Diff line number Diff line change
Expand Up @@ -1316,6 +1316,10 @@ void emitIns_I_AR(instruction ins, emitAttr attr, int val, regNumber reg, int of

void emitIns_R_AR(instruction ins, emitAttr attr, regNumber ireg, regNumber reg, int offs);

void emitIns_Adrp_Ldr_Add(emitAttr attr,
regNumber ireg, regNumber reg2,
ssize_t disp DEBUGARG(size_t targetHandle = 0) DEBUGARG(GenTreeFlags gtFlags = GTF_EMPTY));

void emitIns_R_AI(instruction ins,
emitAttr attr,
regNumber ireg,
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -2176,7 +2176,9 @@ private void getFieldInfo(ref CORINFO_RESOLVED_TOKEN pResolvedToken, CORINFO_MET
else if (field.IsThreadStatic)
{
if ((MethodBeingCompiled.Context.Target.IsWindows && MethodBeingCompiled.Context.Target.Architecture == TargetArchitecture.X64) ||
(MethodBeingCompiled.Context.Target.OperatingSystem == TargetOS.Linux))
((MethodBeingCompiled.Context.Target.OperatingSystem == TargetOS.Linux) &&
((MethodBeingCompiled.Context.Target.Architecture == TargetArchitecture.X64) ||
(MethodBeingCompiled.Context.Target.Architecture == TargetArchitecture.ARM64))))
{
ISortableSymbolNode index = _compilation.NodeFactory.TypeThreadStaticIndex((MetadataType)field.OwningType);
if (index is TypeThreadStaticIndexNode ti)
Expand Down