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a571bf6
Create the `esp32c6-hal` package
jessebraham Jan 5, 2023
a2c6145
Teach `esp-hal-common` about the ESP32-C6
jessebraham Jan 6, 2023
f358cad
Get a number of peripheral drivers building for the ESP32-C6
jessebraham Jan 6, 2023
fc65b3f
Create the `esp32c6-hal` package
jessebraham Jan 5, 2023
bea1242
Simplify and fix the linker script
bjoernQ Jan 20, 2023
5f8e2d1
C6: add I2S
JurajSadel Jan 25, 2023
6db490d
Create the `esp32c6-hal` package
jessebraham Jan 5, 2023
a38ced1
Teach `esp-hal-common` about the ESP32-C6
jessebraham Jan 6, 2023
730f57f
Get a number of peripheral drivers building for the ESP32-C6
jessebraham Jan 6, 2023
3cec8bb
Create the `esp32c6-hal` package
jessebraham Jan 5, 2023
1e5ef3c
C6: update
JurajSadel Jan 20, 2023
e6df68d
Simplify and fix the linker script
bjoernQ Jan 20, 2023
d2b0734
update
JurajSadel Jan 24, 2023
bde4bb5
C6: add I2S
JurajSadel Jan 25, 2023
6351eee
update
JurajSadel Jan 24, 2023
51cb4c0
C6 Interrupts
bjoernQ Jan 25, 2023
753414a
C6: Update build.rs, linker scripts and initial examples
JurajSadel Jan 27, 2023
dece8b4
C6: RMT
JurajSadel Jan 27, 2023
3ad20aa
Fix interrupt handling
bjoernQ Jan 26, 2023
731f1cb
Fix `ClockControl::configure`
bjoernQ Jan 27, 2023
b0e7a59
C6: revert to I2S0 instead of just I2S
JurajSadel Jan 30, 2023
ae4e4b5
C6: rebase and update
JurajSadel Feb 1, 2023
a4edc46
RTC not buildable
JurajSadel Feb 2, 2023
988b1d0
Implement RWDT and SWD disable
bjoernQ Feb 2, 2023
ac4c447
C6: working LEDC
JurajSadel Feb 3, 2023
8ddaf7e
C6: working RMT
JurajSadel Feb 3, 2023
2b7fd7d
C6: add aes
JurajSadel Feb 7, 2023
b100cb2
C6: add mcpwm
JurajSadel Feb 7, 2023
9968157
C6: add rtc_cntln - not finished
JurajSadel Feb 7, 2023
cfb8445
C6: update and formatting
JurajSadel Feb 7, 2023
f9b7e19
C6: add pcnt
JurajSadel Feb 7, 2023
a7e14a9
C6: add examples and format
JurajSadel Feb 7, 2023
b7f0316
Remove inline assembly, fix interrupts and linker scripts
jessebraham Feb 7, 2023
a2e4c93
Remove unused features, update cargo config for atomic emu, misc cleanup
jessebraham Feb 7, 2023
8217147
Get ADC building and example "working" (as much as it ever does)
jessebraham Feb 7, 2023
a933093
Remove a bunch of unused constants which were copied from ESP-IDF
jessebraham Feb 7, 2023
93f926f
The `mcpwm` example now works correctly
jessebraham Feb 7, 2023
59a599d
Get `TWAI` peripheral driver building for C6
jessebraham Feb 8, 2023
46487eb
Clean up the `rtc_cntl` module and get all the other HALs building again
jessebraham Feb 8, 2023
4f97342
Add the C6 to our CI workflow
jessebraham Feb 8, 2023
403c640
Fix various things that have been missed when rebasing
jessebraham Feb 8, 2023
08f6f19
C6: Small updates in wdt (#1)
JurajSadel Feb 9, 2023
730b6b3
Update `esp-println` dependency to fix build errors
jessebraham Feb 9, 2023
e903e90
Fix formatting issues causing pre-commit hook to fail
jessebraham Feb 9, 2023
3622bc1
Get some more examples working
jessebraham Feb 9, 2023
9747426
Working `ram` example
jessebraham Feb 10, 2023
e41ecdd
Sync with changes in `main` after rebasing
jessebraham Feb 10, 2023
28ece39
Working `embassy_spi` example
jessebraham Feb 10, 2023
dd7f469
Use a git dependency for the PAC until we publish a release
jessebraham Feb 10, 2023
7dd27e5
Fix I2S for ESP32-C6
bjoernQ Feb 14, 2023
39444ba
Fix esp32c6 direct boot (#4)
MabezDev Feb 22, 2023
d16cab7
Update RWDT and refactor RTC (#3)
JurajSadel Feb 23, 2023
87cf485
Make required changes to include new `RADIO` peripheral
jessebraham Feb 23, 2023
0d3fd81
Use published versions of PAC and `esp-println`
jessebraham Feb 23, 2023
a381487
Use the correct target extensions (`imac`)
jessebraham Feb 24, 2023
572e99d
Fix the super watchdog timer, plus a few more examples
jessebraham Feb 24, 2023
dc309ea
Fix UART clock configuration
jessebraham Feb 24, 2023
716163b
Make sure to sync UART registers when configuring AT cmd detection
bjoernQ Feb 27, 2023
2f5972b
Disable APM in direct-boot mode
bjoernQ Feb 27, 2023
3eb273a
Address a number of review comments
jessebraham Feb 27, 2023
6641a0d
Fix `SPI` clocks and `rtc_watchdog` example (#6)
JurajSadel Feb 27, 2023
9e5f298
README and example fixes/cleanup
jessebraham Feb 27, 2023
ed59cd9
Add I2C peripheral enable and reset
bjoernQ Feb 27, 2023
e678120
Fix `ApbSarAdc` configuration in `system.rs`
jessebraham Feb 27, 2023
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C6: rebase and update
  • Loading branch information
JurajSadel authored and jessebraham committed Feb 23, 2023
commit ae4e4b5576c8761a96e21d30889da376bf654e55
192 changes: 73 additions & 119 deletions esp-hal-common/src/interrupt/riscv.rs
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,8 @@
//! interrupt15() => Priority::Priority15
//! ```

use riscv::register::mcause;
use esp_riscv_rt::riscv::register::{mcause, mepc, mtvec};
pub use esp_riscv_rt::TrapFrame;

use crate::{
peripherals::{self, Interrupt},
Expand Down Expand Up @@ -538,48 +539,6 @@ mod vectored {
}
}

/// Registers saved in trap handler
#[doc(hidden)]
#[allow(missing_docs)]
#[derive(Debug, Default, Clone, Copy)]
#[repr(C)]
pub struct TrapFrame {
pub ra: usize,
pub t0: usize,
pub t1: usize,
pub t2: usize,
pub t3: usize,
pub t4: usize,
pub t5: usize,
pub t6: usize,
pub a0: usize,
pub a1: usize,
pub a2: usize,
pub a3: usize,
pub a4: usize,
pub a5: usize,
pub a6: usize,
pub a7: usize,
pub s0: usize,
pub s1: usize,
pub s2: usize,
pub s3: usize,
pub s4: usize,
pub s5: usize,
pub s6: usize,
pub s7: usize,
pub s8: usize,
pub s9: usize,
pub s10: usize,
pub s11: usize,
pub gp: usize,
pub tp: usize,
pub sp: usize,
pub pc: usize,
pub mstatus: usize,
pub mcause: usize,
pub mtval: usize,
}

/// # Safety
///
Expand All @@ -595,10 +554,10 @@ pub unsafe extern "C" fn start_trap_rust_hal(trap_frame: *mut TrapFrame) {

let cause = mcause::read();
if cause.is_exception() {
let pc = riscv::register::mepc::read();
let pc = mepc::read();
handle_exception(pc, trap_frame);
} else {
let code = riscv::register::mcause::read().code();
let code = mcause::read().code();
match code {
1 => interrupt1(trap_frame.as_mut().unwrap()),
2 => interrupt2(trap_frame.as_mut().unwrap()),
Expand Down Expand Up @@ -656,80 +615,75 @@ unsafe fn handle_exception(pc: usize, trap_frame: *mut TrapFrame) {
return;
}

extern "C" {
pub fn _start_trap_atomic_rust(trap_frame: *mut riscv_atomic_emulation_trap::TrapFrame);
}

let mut atomic_emulation_trap_frame = riscv_atomic_emulation_trap::TrapFrame {
x0: 0,
ra: (*trap_frame).ra,
sp: (*trap_frame).sp,
gp: (*trap_frame).gp,
tp: (*trap_frame).tp,
t0: (*trap_frame).t0,
t1: (*trap_frame).t1,
t2: (*trap_frame).t2,
fp: (*trap_frame).s0,
s1: (*trap_frame).s1,
a0: (*trap_frame).a0,
a1: (*trap_frame).a1,
a2: (*trap_frame).a2,
a3: (*trap_frame).a3,
a4: (*trap_frame).a4,
a5: (*trap_frame).a5,
a6: (*trap_frame).a6,
a7: (*trap_frame).a7,
s2: (*trap_frame).s2,
s3: (*trap_frame).s3,
s4: (*trap_frame).s4,
s5: (*trap_frame).s5,
s6: (*trap_frame).s6,
s7: (*trap_frame).s7,
s8: (*trap_frame).s8,
s9: (*trap_frame).s9,
s10: (*trap_frame).s10,
s11: (*trap_frame).s11,
t3: (*trap_frame).t3,
t4: (*trap_frame).t4,
t5: (*trap_frame).t5,
t6: (*trap_frame).t6,
pc: (*trap_frame).pc,
};
let mut frame = [
0,
(*trap_frame).ra,
(*trap_frame).sp,
(*trap_frame).gp,
(*trap_frame).tp,
(*trap_frame).t0,
(*trap_frame).t1,
(*trap_frame).t2,
(*trap_frame).s0,
(*trap_frame).s1,
(*trap_frame).a0,
(*trap_frame).a1,
(*trap_frame).a2,
(*trap_frame).a3,
(*trap_frame).a4,
(*trap_frame).a5,
(*trap_frame).a6,
(*trap_frame).a7,
(*trap_frame).s2,
(*trap_frame).s3,
(*trap_frame).s4,
(*trap_frame).s5,
(*trap_frame).s6,
(*trap_frame).s7,
(*trap_frame).s8,
(*trap_frame).s9,
(*trap_frame).s10,
(*trap_frame).s11,
(*trap_frame).t3,
(*trap_frame).t4,
(*trap_frame).t5,
(*trap_frame).t6,
];

_start_trap_atomic_rust(&mut atomic_emulation_trap_frame);

(*trap_frame).pc = atomic_emulation_trap_frame.pc;
(*trap_frame).ra = atomic_emulation_trap_frame.ra;
(*trap_frame).sp = atomic_emulation_trap_frame.sp;
(*trap_frame).gp = atomic_emulation_trap_frame.gp;
(*trap_frame).tp = atomic_emulation_trap_frame.tp;
(*trap_frame).t0 = atomic_emulation_trap_frame.t0;
(*trap_frame).t1 = atomic_emulation_trap_frame.t1;
(*trap_frame).t2 = atomic_emulation_trap_frame.t2;
(*trap_frame).s0 = atomic_emulation_trap_frame.fp;
(*trap_frame).s1 = atomic_emulation_trap_frame.s1;
(*trap_frame).a0 = atomic_emulation_trap_frame.a0;
(*trap_frame).a1 = atomic_emulation_trap_frame.a1;
(*trap_frame).a2 = atomic_emulation_trap_frame.a2;
(*trap_frame).a3 = atomic_emulation_trap_frame.a3;
(*trap_frame).a4 = atomic_emulation_trap_frame.a4;
(*trap_frame).a5 = atomic_emulation_trap_frame.a5;
(*trap_frame).a6 = atomic_emulation_trap_frame.a6;
(*trap_frame).a7 = atomic_emulation_trap_frame.a7;
(*trap_frame).s2 = atomic_emulation_trap_frame.s2;
(*trap_frame).s3 = atomic_emulation_trap_frame.s3;
(*trap_frame).s4 = atomic_emulation_trap_frame.s4;
(*trap_frame).s5 = atomic_emulation_trap_frame.s5;
(*trap_frame).s6 = atomic_emulation_trap_frame.s6;
(*trap_frame).s7 = atomic_emulation_trap_frame.s7;
(*trap_frame).s8 = atomic_emulation_trap_frame.s8;
(*trap_frame).s9 = atomic_emulation_trap_frame.s9;
(*trap_frame).s10 = atomic_emulation_trap_frame.s10;
(*trap_frame).s11 = atomic_emulation_trap_frame.s11;
(*trap_frame).t3 = atomic_emulation_trap_frame.t3;
(*trap_frame).t4 = atomic_emulation_trap_frame.t4;
(*trap_frame).t5 = atomic_emulation_trap_frame.t5;
(*trap_frame).t6 = atomic_emulation_trap_frame.t6;
riscv_atomic_emulation_trap::atomic_emulation((*trap_frame).pc, &mut frame);

(*trap_frame).ra = frame[1];
(*trap_frame).sp = frame[2];
(*trap_frame).gp = frame[3];
(*trap_frame).tp = frame[4];
(*trap_frame).t0 = frame[5];
(*trap_frame).t1 = frame[6];
(*trap_frame).t2 = frame[7];
(*trap_frame).s0 = frame[8];
(*trap_frame).s1 = frame[9];
(*trap_frame).a0 = frame[10];
(*trap_frame).a1 = frame[11];
(*trap_frame).a2 = frame[12];
(*trap_frame).a3 = frame[13];
(*trap_frame).a4 = frame[14];
(*trap_frame).a5 = frame[15];
(*trap_frame).a6 = frame[16];
(*trap_frame).a7 = frame[17];
(*trap_frame).s2 = frame[18];
(*trap_frame).s3 = frame[19];
(*trap_frame).s4 = frame[20];
(*trap_frame).s5 = frame[21];
(*trap_frame).s6 = frame[22];
(*trap_frame).s7 = frame[23];
(*trap_frame).s8 = frame[24];
(*trap_frame).s9 = frame[25];
(*trap_frame).s10 = frame[26];
(*trap_frame).s11 = frame[27];
(*trap_frame).t3 = frame[28];
(*trap_frame).t4 = frame[29];
(*trap_frame).t5 = frame[30];
(*trap_frame).t6 = frame[31];
(*trap_frame).pc = pc + 4;
}

#[doc(hidden)]
Expand All @@ -741,7 +695,7 @@ pub fn _setup_interrupts() {

unsafe {
let vec_table = &_vector_table_hal as *const _ as usize;
riscv::register::mtvec::write(vec_table, riscv::register::mtvec::TrapMode::Vectored);
mtvec::write(vec_table, mtvec::TrapMode::Vectored);

#[cfg(feature = "vectored")]
crate::interrupt::init_vectoring();
Expand Down
6 changes: 3 additions & 3 deletions esp-hal-common/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -70,7 +70,7 @@ pub use self::pulse_control::PulseControl;
// timer::Timer,
// uart::Uart,
// };
pub use self::{delay::Delay, gpio::*, interrupt::*, spi::Spi, timer::Timer, uart::Uart};
pub use self::{delay::Delay, gpio::*, interrupt::*, spi::Spi, timer::Timer, uart::Uart, /*rtc_cntl::{Rtc, Rwdt},*/};

// pub mod analog;
pub mod clock;
Expand All @@ -97,8 +97,8 @@ pub mod pulse_control;
pub mod radio;
pub mod rng;
pub mod rom;
#[cfg(not(esp32c6))]
pub mod rtc_cntl;
// #[cfg(not(esp32c6))]
// pub mod rtc_cntl;
pub mod sha;
pub mod spi;
pub mod system;
Expand Down
59 changes: 0 additions & 59 deletions esp-hal-common/src/system.rs
Original file line number Diff line number Diff line change
Expand Up @@ -80,11 +80,7 @@ impl PeripheralClockControl {
)
};

<<<<<<< HEAD
#[cfg(any(esp32c2, esp32c3, esp32c6, esp32s2, esp32s3))]
=======
#[cfg(any(esp32c2, esp32c3, esp32c6, esp32s3))]
>>>>>>> b278bca (Get a number of peripheral drivers building for the ESP32-C6)
let (perip_clk_en1, perip_rst_en1) = { (&system.perip_clk_en1, &system.perip_rst_en1) };

match peripheral {
Expand Down Expand Up @@ -253,61 +249,6 @@ impl PeripheralClockControl {
}
}

#[cfg(esp32c6)]
impl PeripheralClockControl {
/// Enables and resets the given peripheral
pub fn enable(&mut self, peripheral: Peripheral) {
let system = unsafe { &*SystemPeripheral::PTR };

match peripheral {
Peripheral::Spi2 => {
system.spi2_conf.modify(|_, w| w.spi2_clk_en().set_bit());
system.spi2_conf.modify(|_, w| w.spi2_rst_en().clear_bit());
}
Peripheral::I2cExt0 => {
// FIXME
// perip_clk_en0.modify(|_, w| w.i2c_ext0_clk_en().set_bit());
// perip_rst_en0.modify(|_, w| w.i2c_ext0_rst().clear_bit());
}
Peripheral::Rmt => {
system.rmt_conf.modify(|_, w| w.rmt_clk_en().set_bit());
system.rmt_conf.modify(|_, w| w.rmt_rst_en().clear_bit());
}
Peripheral::Ledc => {
system.ledc_conf.modify(|_, w| w.ledc_clk_en().set_bit());
system.ledc_conf.modify(|_, w| w.ledc_rst_en().clear_bit());
}
Peripheral::Mcpwm0 | Peripheral::Mcpwm1 => {
system.pwm_conf.modify(|_, w| w.pwm_clk_en().set_bit());
system.pwm_conf.modify(|_, w| w.pwm_rst_en().clear_bit());
}
Peripheral::ApbSarAdc => {
// TODO
}
Peripheral::Gdma => {
system.gdma_conf.modify(|_, w| w.gdma_clk_en().set_bit());
system.gdma_conf.modify(|_, w| w.gdma_rst_en().clear_bit());
}
Peripheral::I2s0 => {
system.i2s_conf.modify(|_, w| w.i2s_clk_en().set_bit());
system.i2s_conf.modify(|_, w| w.i2s_rst_en().clear_bit());
}
Peripheral::Twai0 => {
system.twai0_conf.modify(|_, w| w.twai0_clk_en().set_bit());
system
.twai0_conf
.modify(|_, w| w.twai0_rst_en().clear_bit());
}
Peripheral::Twai1 => {
system.twai1_conf.modify(|_, w| w.twai1_clk_en().set_bit());
system
.twai1_conf
.modify(|_, w| w.twai1_rst_en().clear_bit());
}
}
}
}

/// Controls the configuration of the chip's clocks.
pub struct SystemClockControl {
_private: (),
Expand Down
14 changes: 9 additions & 5 deletions esp32c6-hal/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,7 @@ version = "0.1.0"
authors = [
"Jesse Braham <[email protected]>",
"Björn Quentin <[email protected]>",
"Juraj Sadel <[email protected]>",
]
edition = "2021"
rust-version = "1.60.0"
Expand All @@ -29,15 +30,15 @@ cfg-if = "1.0.0"
embassy-time = { version = "0.1.0", features = ["nightly"], optional = true }
embedded-hal = { version = "0.2.7", features = ["unproven"] }
embedded-hal-1 = { version = "=1.0.0-alpha.9", optional = true, package = "embedded-hal" }
embedded-hal-async = { version = "0.1.0-alpha.3", optional = true }
embedded-hal-async = { version = "0.2.0-alpha.0", optional = true }
embedded-hal-nb = { version = "=1.0.0-alpha.1", optional = true }
embedded-can = { version = "0.4.1", optional = true }
esp-hal-common = { features = ["esp32c6"], path = "../esp-hal-common" }
esp-hal-common = { version = "0.5.0", features = ["esp32c6"], path = "../esp-hal-common" }
esp-riscv-rt = { version = "0.1.0", optional = true }
r0 = "1.0.0"
riscv = "0.10.1"
riscv-rt = { version = "0.11.0", optional = true }

[dev-dependencies]
aes = "0.8.2"
critical-section = "1.1.1"
embassy-executor = { package = "embassy-executor", git = "https://github.com/embassy-rs/embassy/", rev = "cd9a65b", features = ["nightly", "integrated-timers"] }
embedded-graphics = "0.7.1"
Expand All @@ -53,7 +54,7 @@ default = ["rt", "vectored"]
mcu-boot = []
direct-boot = []
eh1 = ["esp-hal-common/eh1", "dep:embedded-hal-1", "dep:embedded-hal-nb", "dep:embedded-can"]
rt = ["riscv-rt"]
rt = ["esp-riscv-rt"]
smartled = ["esp-hal-common/smartled"]
ufmt = ["esp-hal-common/ufmt"]
vectored = ["esp-hal-common/vectored"]
Expand All @@ -78,3 +79,6 @@ embassy-time-timg0 = ["esp-hal-common/embassy-time-timg0", "embassy-time/tick-hz
# [[example]]
# name = "embassy_hello_world"
# required-features = ["embassy"]

[profile.dev]
opt-level = 1
3 changes: 2 additions & 1 deletion esp32c6-hal/examples/blinky.rs
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,8 @@ use esp32c6_hal::{
Delay,
};
use esp_backtrace as _;
use riscv_rt::entry;
use esp_riscv_rt::entry;


#[entry]
fn main() -> ! {
Expand Down
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