Update RWDT and refactor RTC (#3)

* C6: Update RWDT and add example, refactor RTC and add not-really-good example * Update based on review comments, resolve bunch of warnings and run cargo fmt * Update C6 esp-pacs rev commit * Fix clocks_ll/esp32c6.rs * Fix riscv interrupts * Remove clock_monitor example for now * RAM example works in direct-boot mode * Add a TODO for &mut TIMG0 and cargo fmt * Fix linker script after a bad rebase * Update CI and Cargo.toml embassy required features * use riscv32imac-unknown-none-elf target for C6 in CI * change default target to riscv32imac-unknown-none-elf * add riscv32imac-unknown-none-elf target to MSRV job * another cleanup --------- Co-authored-by: bjoernQ <[email protected]> Co-authored-by: Jesse Braham <[email protected]>
esp-rs · jessebraham · Feb 27, 2023 · Jan 5, 2023 · Jan 6, 2023 · Jan 6, 2023
commit d16cab70a9b941eb9de8ccbc882b04ca0fa8cded
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -108,11 +108,11 @@ jobs:
       # Subsequent steps can just check the examples instead, as we're already
       # confident that they link.
       - name: check esp32c3-hal (common features)
-        run: cargo check --manifest-path=esp32c3-hal/Cargo.toml --target=riscv32imc-unknown-none-elf --examples --features=eh1,smartled,ufmt
+        run: cd esp32c3-hal/ && cargo check --examples --features=eh1,smartled,ufmt
       - name: check esp32c3-hal (async, systick)
-        run: cargo check --manifest-path=esp32c3-hal/Cargo.toml --target=riscv32imc-unknown-none-elf --example=embassy_hello_world --features=embassy,embassy-time-systick
+        run: cd esp32c3-hal/ && cargo check --example=embassy_hello_world --features=embassy,embassy-time-systick
       - name: check esp32c3-hal (async, timg0)
-        run: cargo check --manifest-path=esp32c3-hal/Cargo.toml --target=riscv32imc-unknown-none-elf --example=embassy_hello_world --features=embassy,embassy-time-timg0
+        run: cd esp32c3-hal/ && cargo check --example=embassy_hello_world --features=embassy,embassy-time-timg0
       - name: check esp32c3-hal (async, gpio)
         run: cd esp32c3-hal/ && cargo check --example=embassy_wait --features=embassy,embassy-time-systick,async
       - name: check esp32c3-hal (async, spi)
@@ -125,7 +125,7 @@ jobs:
       - uses: actions/checkout@v3
       - uses: dtolnay/rust-toolchain@v1
         with:
-          target: riscv32imc-unknown-none-elf
+          target: riscv32imac-unknown-none-elf
           toolchain: nightly
           components: rust-src
       - uses: Swatinem/rust-cache@v2
@@ -141,7 +141,7 @@ jobs:
       # Subsequent steps can just check the examples instead, as we're already
       # confident that they link.
       - name: check esp32c6-hal (common features)
-        run: cd esp32c6-hal/ && cargo check --examples --features=eh1,ufmt
+        run: cd esp32c6-hal/ && cargo check --examples --features=eh1,smartled,ufmt
       - name: check esp32c6-hal (async, systick)
         run: cd esp32c6-hal/ && cargo check --example=embassy_hello_world --features=embassy,embassy-time-systick
       - name: check esp32c6-hal (async, timg0)
@@ -213,7 +213,6 @@ jobs:
         run: cd esp32s3-hal/ && cargo check --example=embassy_wait --features=embassy,embassy-time-timg0,async
       - name: check esp32s3-hal (async, spi)
         run: cd esp32s3-hal/ && cargo check --example=embassy_spi --features=embassy,embassy-time-timg0,async
-
   # --------------------------------------------------------------------------
   # MSRV
 
@@ -224,7 +223,7 @@ jobs:
       - uses: actions/checkout@v3
       - uses: dtolnay/rust-toolchain@v1
         with:
-          target: riscv32imc-unknown-none-elf
+          target: riscv32imc-unknown-none-elf, riscv32imac-unknown-none-elf
           toolchain: "1.65.0"
       - uses: Swatinem/rust-cache@v2
 
@@ -329,4 +328,4 @@ jobs:
       - name: rustfmt (esp32s2-hal)
         run: cargo fmt --all --manifest-path=esp32s2-hal/Cargo.toml -- --check
       - name: rustfmt (esp32s3-hal)
-        run: cargo fmt --all --manifest-path=esp32s3-hal/Cargo.toml -- --check
+        run: cargo fmt --all --manifest-path=esp32s3-hal/Cargo.toml -- --check
diff --git a/esp-hal-common/Cargo.toml b/esp-hal-common/Cargo.toml
@@ -56,7 +56,7 @@ ufmt-write = { version = "0.1.0", optional = true }
 esp32   = { version = "0.21.0", features = ["critical-section"], optional = true }
 esp32c2 = { version = "0.8.0",  features = ["critical-section"], optional = true }
 esp32c3 = { version = "0.11.0", features = ["critical-section"], optional = true }
-esp32c6 = { git = "https://github.com/esp-rs/esp-pacs", rev = "b5a7f1a", package = "esp32c6", features = ["critical-section"], optional = true }
+esp32c6 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1124275", package = "esp32c6", features = ["critical-section"], optional = true }
 esp32s2 = { version = "0.12.0", features = ["critical-section"], optional = true }
 esp32s3 = { version = "0.15.0", features = ["critical-section"], optional = true }
 

diff --git a/esp-hal-common/src/clock/clocks_ll/esp32c6.rs b/esp-hal-common/src/clock/clocks_ll/esp32c6.rs
@@ -41,7 +41,7 @@ const MODEM_LPCON_CLK_I2C_MST_FO: u32 = 1 << 2;
 const MODEM_LPCON_I2C_MST_CLK_CONF_REG: u32 = DR_REG_MODEM_LPCON_BASE + 0x10;
 const MODEM_LPCON_CLK_I2C_MST_SEL_160M: u32 = 1 << 0;
 
-pub(crate) fn esp32c6_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock) {
+pub(crate) fn esp32c6_rtc_bbpll_configure(_xtal_freq: XtalClock, _pll_freq: PllClock) {
     unsafe {
         // enable i2c mst clk by force on temporarily
         (MODEM_LPCON_CLK_CONF_FORCE_ON_REG as *mut u32).write_volatile(
@@ -278,6 +278,8 @@ const LP_I2C_ANA_MST_I2C0_DATA_REG: u32 = DR_REG_LP_I2C_ANA_MST_BASE + 0x8;
 const LP_I2C_ANA_MST_I2C0_RDATA_V: u32 = 0x000000FF;
 const LP_I2C_ANA_MST_I2C0_RDATA_S: u32 = 0;
 
+const REGI2C_BBPLL: u8 = 0x66;
+
 fn regi2c_enable_block(block: u8) {
     reg_set_bit(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
     reg_set_bit(LP_I2C_ANA_MST_DATE_REG, LP_I2C_ANA_MST_I2C_MAT_CLK_EN);
@@ -324,7 +326,7 @@ fn regi2c_disable_block(block: u8) {
     }
 }
 
-pub(crate) fn regi2c_write(block: u8, host_id: u8, reg_add: u8, data: u8) {
+pub(crate) fn regi2c_write(block: u8, _host_id: u8, reg_add: u8, data: u8) {
     regi2c_enable_block(block);
 
     let temp: u32 = ((block as u32 & REGI2C_RTC_SLAVE_ID_V as u32) << REGI2C_RTC_SLAVE_ID_S as u32)
@@ -337,7 +339,7 @@ pub(crate) fn regi2c_write(block: u8, host_id: u8, reg_add: u8, data: u8) {
     regi2c_disable_block(block);
 }
 
-pub(crate) fn regi2c_write_mask(block: u8, host_id: u8, reg_add: u8, msb: u8, lsb: u8, data: u8) {
+pub(crate) fn regi2c_write_mask(block: u8, _host_id: u8, reg_add: u8, msb: u8, lsb: u8, data: u8) {
     assert!(msb - lsb < 8);
     regi2c_enable_block(block);
 

diff --git a/esp-hal-common/src/interrupt/riscv.rs b/esp-hal-common/src/interrupt/riscv.rs
@@ -330,15 +330,15 @@ mod vectored {
         for (prio, num) in PRIORITY_TO_INTERRUPT.iter().enumerate() {
             set_kind(
                 crate::get_core(),
-                core::mem::transmute(*num),
+                core::mem::transmute(*num as u32),
                 InterruptKind::Level,
             );
             set_priority(
                 crate::get_core(),
-                core::mem::transmute(*num),
+                core::mem::transmute(*num as u32),
                 core::mem::transmute((prio as u8) + 1),
             );
-            enable_cpu_interrupt(core::mem::transmute(*num));
+            enable_cpu_interrupt(core::mem::transmute(*num as u32));
         }
     }
 

diff --git a/esp-hal-common/src/ledc/channel.rs b/esp-hal-common/src/ledc/channel.rs
@@ -197,10 +197,10 @@ macro_rules! start_duty_without_fading {
 macro_rules! start_duty_without_fading {
     ($self: ident, $num: literal) => {
         paste! {
-            $self.ledc.[<ch $num _conf1>].write(|w| unsafe {
+            $self.ledc.[<ch $num _conf1>].write(|w|
                 w.[<duty_start>]()
                     .set_bit()
-            });
+            );
             $self.ledc.[<ch $num _gamma_wr>].write(|w| unsafe {
                 w.[<ch_gamma_duty_inc>]()
                     .set_bit()

diff --git a/esp-hal-common/src/pulse_control.rs b/esp-hal-common/src/pulse_control.rs
@@ -937,7 +937,7 @@ macro_rules! rmt {
             pcr.rmt_sclk_conf.write(|w| w.sclk_en().set_bit());
 
 
-            self.reg.sys_conf.modify(|_, w| unsafe {
+            self.reg.sys_conf.modify(|_, w|
                 // Enable clock
                 w.clk_en()
                     .set_bit()
@@ -952,7 +952,7 @@ macro_rules! rmt {
                     .clear_bit()
                     // Disable FIFO mode
                     .apb_fifo_mask()
-                    .set_bit() });
+                    .set_bit());
                     // Select clock source
                 #[cfg(not(esp32c6))]
                 self.reg.sys_conf.modify(|_, w| unsafe {

diff --git a/esp-hal-common/src/rtc_cntl/mod.rs b/esp-hal-common/src/rtc_cntl/mod.rs
@@ -1,15 +1,18 @@
 use embedded_hal::watchdog::{Watchdog, WatchdogDisable, WatchdogEnable};
-use fugit::{HertzU32, MicrosDurationU64};
+#[cfg(not(esp32c6))]
+use fugit::HertzU32;
+use fugit::MicrosDurationU64;
 
 use self::rtc::SocResetReason;
-#[cfg(not(any(esp32)))]
+#[cfg(not(esp32c6))]
+use crate::clock::{Clock, XtalClock};
+#[cfg(not(any(esp32, esp32c6)))]
 use crate::efuse::Efuse;
 #[cfg(esp32c6)]
-use crate::peripherals::{LP_AON, LP_CLKRST, LP_WDT, PMU};
+use crate::peripherals::LP_WDT;
 #[cfg(not(esp32c6))]
 use crate::peripherals::{RTC_CNTL, TIMG0};
 use crate::{
-    clock::{Clock, XtalClock},
     peripheral::{Peripheral, PeripheralRef},
     Cpu,
 };
@@ -27,11 +30,16 @@ type RtcCntl = crate::peripherals::RTC_CNTL;
 #[cfg_attr(esp32s3, path = "rtc/esp32s3.rs")]
 mod rtc;
 
+#[cfg(esp32c6)]
+pub use rtc::RtcClock;
+
 extern "C" {
+    #[allow(dead_code)]
     fn ets_delay_us(us: u32);
     fn rtc_get_reset_reason(cpu_num: u32) -> u32;
 }
 
+#[cfg(not(esp32c6))]
 #[allow(unused)]
 #[derive(Debug, Clone, Copy)]
 /// RTC SLOW_CLK frequency values
@@ -42,6 +50,7 @@ pub(crate) enum RtcFastClock {
     RtcFastClock8m     = 1,
 }
 
+#[cfg(not(esp32c6))]
 impl Clock for RtcFastClock {
     fn frequency(&self) -> HertzU32 {
         match self {
@@ -55,6 +64,7 @@ impl Clock for RtcFastClock {
 }
 
 #[cfg(not(esp32c6))]
+#[allow(unused)]
 #[derive(Debug, Clone, Copy)]
 /// RTC SLOW_CLK frequency values
 pub(crate) enum RtcSlowClock {
@@ -66,21 +76,7 @@ pub(crate) enum RtcSlowClock {
     RtcSlowClock8mD256  = 2,
 }
 
-#[cfg(esp32c6)]
-#[derive(Debug, Clone, Copy, PartialEq)]
-/// RTC SLOW_CLK frequency values
-pub(crate) enum RtcSlowClock {
-    /// Internal slow RC oscillator
-    RtcSlowClockRtc     = 0,
-    /// External 32 KHz XTAL
-    RtcSlowClock32kXtal = 1,
-    /// TODO
-    RtcSlowClock32kRc   = 2,
-    /// Internal 150 KHz RC oscillator
-    RtcCalInternalOsc   = 3,
-    RtcCalRcFast,
-}
-
+#[cfg(not(esp32c6))]
 impl Clock for RtcSlowClock {
     fn frequency(&self) -> HertzU32 {
         match self {
@@ -120,35 +116,10 @@ pub(crate) enum RtcCalSel {
     RtcCalInternalOsc = 3,
 }
 
-#[cfg(esp32c6)]
-#[derive(Debug, Clone, Copy, PartialEq)]
-/// Clock source to be calibrated using rtc_clk_cal function
-pub(crate) enum RtcCalSel {
-    /// Currently selected RTC SLOW_CLK
-    RtcCalRtcMux      = -1,
-    /// Currently selected RTC SLOW_CLK
-    RtcCalRcSlow      = 0,
-    /// External 32 KHz XTAL
-    RtcCal32kXtal     = 1,
-    /// TODO
-    RtcCal32kRc       = 2,
-    #[cfg(not(esp32))]
-    /// Internal 150 KHz RC oscillator TODO
-    RtcCalInternalOsc = 3,
-    RtcCalRcFast,
-}
-
-#[cfg(esp32c6)]
-pub(crate) enum RtcCaliClkSel {
-    CaliClkRcSlow = 0,
-    CaliClkRcFast = 1,
-    CaliClk32k    = 2,
-}
-
 pub struct Rtc<'d> {
     _inner: PeripheralRef<'d, RtcCntl>,
     pub rwdt: Rwdt,
-    #[cfg(any(esp32c2, esp32c3, esp32c6, esp32s3))]
+    #[cfg(any(esp32c2, esp32c3, esp32s3, esp32c6))]
     pub swd: Swd,
 }
 
@@ -160,7 +131,7 @@ impl<'d> Rtc<'d> {
         Self {
             _inner: rtc_cntl.into_ref(),
             rwdt: Rwdt::default(),
-            #[cfg(any(esp32c2, esp32c3, esp32c6, esp32s3))]
+            #[cfg(any(esp32c2, esp32c3, esp32s3, esp32c6))]
             swd: Swd::new(),
         }
     }
@@ -170,9 +141,11 @@ impl<'d> Rtc<'d> {
     }
 }
 
+#[cfg(not(esp32c6))]
 /// RTC Watchdog Timer
 pub struct RtcClock;
 
+#[cfg(not(esp32c6))]
 /// RTC Watchdog Timer driver
 impl RtcClock {
     const CAL_FRACT: u32 = 19;