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feat(riscv): relocate .trap machinery to RAM
#541
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Previously, the trap vector itself and its immediate callees (`_start_trap` and `_start_trap_rust_hal`) were located in the mapped instruction flash range `0x420..`, increasing cache pressure and adding variable latency to the very beginning of the interrupt/exception service flow. This change places those routines in iram directly: ``` Num: Value Size Type Bind Vis Ndx Name 48177: 40380280 2428 FUNC GLOBAL DEFAULT 6 _start_trap_rust_hal 48197: 40380bfc 54 FUNC GLOBAL DEFAULT 6 _start_trap_rust 48265: 40380200 0 FUNC GLOBAL DEFAULT 6 _vector_table 48349: 40380100 0 NOTYPE GLOBAL DEFAULT 6 default_start_trap 48350: 40380100 0 NOTYPE GLOBAL DEFAULT 6 _start_trap ``` As seen via `readelf -W -s -C ./target/riscv32imc-unknown-none-elf/debug/examples/gpio_interrupt | grep -E _start_trap\|_vector\|Ndx`
This change follows through on relocating the `_vector_table`, `_start_trap`, and `_start_trap_rust` functions for all present build/link modes for the 'c2, 'c3, 'c6, and 'h2. It has been tested by running the `software_interrupts` example for the 'c3 in direct-boot and esp-bootloader contexts, but I wasn't able to identify how to run the `mcu-boot` mode for the 'c3, nor do I have present access to any of the other devices for testing.
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Hmm, I'm not sure whether to add a CHANGELOG entry. I see at the top that it says:
Seems like we ought to either remove that caveat or update the changelog CI action to reflect it. What do you think? |
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.trap machinery to RAM
MabezDev
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So it looks like this change moves about 2775 bytes into RAM. I don't think that will a be a huge deal, especially since the hal trap function is actually taking up most of that:
riscv32-esp-elf-objdump -t target/riscv32imc-unknown-none-elf/release/examples/software_interrupts| grep start_trap_rust_hal
40380880 g F .trap 0000095a _start_trap_rust_hal
I imagine improvements in other PRs will reduce this usage quite a bit.
In my opinion this LGTM. Will let @bjoernQ voice any concerns about the memory usage if he wants.
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I guess 2775 bytes should be okay. If this becomes a problem in future, we can still make it an opt-out feature But I have no idea why the changelog-check still fails with the label 🤔 On the other hand probably this is really a change that deserves a changelog-entry in the "changed" section |
I agree, @sethp would you mind adding a quick changelog entry under the "changed" section? |
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Yeah for sure: sorry for the confusion, I was just thrown by the "only changes to esp-hal-common" bit when this doesn't actually touch that directory at all. |
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Also, I'm totally on board for gating this somehow, I'm just not sure what that looks like with linker scripts. A change to the But if y'all want that, I'm happy to take it on: just let me know! |
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* feat: relocate riscv isr to iram Previously, the trap vector itself and its immediate callees (`_start_trap` and `_start_trap_rust_hal`) were located in the mapped instruction flash range `0x420..`, increasing cache pressure and adding variable latency to the very beginning of the interrupt/exception service flow. This change places those routines in iram directly: ``` Num: Value Size Type Bind Vis Ndx Name 48177: 40380280 2428 FUNC GLOBAL DEFAULT 6 _start_trap_rust_hal 48197: 40380bfc 54 FUNC GLOBAL DEFAULT 6 _start_trap_rust 48265: 40380200 0 FUNC GLOBAL DEFAULT 6 _vector_table 48349: 40380100 0 NOTYPE GLOBAL DEFAULT 6 default_start_trap 48350: 40380100 0 NOTYPE GLOBAL DEFAULT 6 _start_trap ``` As seen via `readelf -W -s -C ./target/riscv32imc-unknown-none-elf/debug/examples/gpio_interrupt | grep -E _start_trap\|_vector\|Ndx` * feat(riscv): place .trap in RAM This change follows through on relocating the `_vector_table`, `_start_trap`, and `_start_trap_rust` functions for all present build/link modes for the 'c2, 'c3, 'c6, and 'h2. It has been tested by running the `software_interrupts` example for the 'c3 in direct-boot and esp-bootloader contexts, but I wasn't able to identify how to run the `mcu-boot` mode for the 'c3, nor do I have present access to any of the other devices for testing. * docs: Update CHANGELOG.md
* feat: relocate riscv isr to iram Previously, the trap vector itself and its immediate callees (`_start_trap` and `_start_trap_rust_hal`) were located in the mapped instruction flash range `0x420..`, increasing cache pressure and adding variable latency to the very beginning of the interrupt/exception service flow. This change places those routines in iram directly: ``` Num: Value Size Type Bind Vis Ndx Name 48177: 40380280 2428 FUNC GLOBAL DEFAULT 6 _start_trap_rust_hal 48197: 40380bfc 54 FUNC GLOBAL DEFAULT 6 _start_trap_rust 48265: 40380200 0 FUNC GLOBAL DEFAULT 6 _vector_table 48349: 40380100 0 NOTYPE GLOBAL DEFAULT 6 default_start_trap 48350: 40380100 0 NOTYPE GLOBAL DEFAULT 6 _start_trap ``` As seen via `readelf -W -s -C ./target/riscv32imc-unknown-none-elf/debug/examples/gpio_interrupt | grep -E _start_trap\|_vector\|Ndx` * feat(riscv): place .trap in RAM This change follows through on relocating the `_vector_table`, `_start_trap`, and `_start_trap_rust` functions for all present build/link modes for the 'c2, 'c3, 'c6, and 'h2. It has been tested by running the `software_interrupts` example for the 'c3 in direct-boot and esp-bootloader contexts, but I wasn't able to identify how to run the `mcu-boot` mode for the 'c3, nor do I have present access to any of the other devices for testing. * docs: Update CHANGELOG.md
* feat: relocate riscv isr to iram Previously, the trap vector itself and its immediate callees (`_start_trap` and `_start_trap_rust_hal`) were located in the mapped instruction flash range `0x420..`, increasing cache pressure and adding variable latency to the very beginning of the interrupt/exception service flow. This change places those routines in iram directly: ``` Num: Value Size Type Bind Vis Ndx Name 48177: 40380280 2428 FUNC GLOBAL DEFAULT 6 _start_trap_rust_hal 48197: 40380bfc 54 FUNC GLOBAL DEFAULT 6 _start_trap_rust 48265: 40380200 0 FUNC GLOBAL DEFAULT 6 _vector_table 48349: 40380100 0 NOTYPE GLOBAL DEFAULT 6 default_start_trap 48350: 40380100 0 NOTYPE GLOBAL DEFAULT 6 _start_trap ``` As seen via `readelf -W -s -C ./target/riscv32imc-unknown-none-elf/debug/examples/gpio_interrupt | grep -E _start_trap\|_vector\|Ndx` * feat(riscv): place .trap in RAM This change follows through on relocating the `_vector_table`, `_start_trap`, and `_start_trap_rust` functions for all present build/link modes for the 'c2, 'c3, 'c6, and 'h2. It has been tested by running the `software_interrupts` example for the 'c3 in direct-boot and esp-bootloader contexts, but I wasn't able to identify how to run the `mcu-boot` mode for the 'c3, nor do I have present access to any of the other devices for testing. * docs: Update CHANGELOG.md
This change follows through on relocating the
_vector_table,_start_trap, and_start_trap_rustfunctions for all present build/link modes for the 'c2, 'c3, 'c6, and 'h2.It has been tested by running the
software_interruptsexample for the 'c3 in direct-boot and esp-bootloader contexts, but I wasn't able to identify how to run themcu-bootmode for the 'c3, nor do I have present access to any of the other devices for testing.Must
errorsorwarnings.Timer0::stealfor all devices andRtcFastClockXtalD2for the 'h2cargo fmtwas run.CHANGELOG.mdin the proper section.Nice to have