Fix insertion location of trap section in ram

[MabezDev]

Although it shouldn't matter where the trap section is located in IRAM, it seems it does. Placing it before other IRAM items seems to resolve #604.

Must

• The code compiles without errors or warnings.
• All examples work.
• cargo fmt was run.
• Your changes were added to the CHANGELOG.md in the proper section.
• You updated existing examples or added examples (if applicable).
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Nice to have

• You add a description of your work to this PR.
• You added proper docs for your newly added features and code.

Closes #604

[bjoernQ]

This will fix the problem of esp-wifi not working anymore with the latest HAL 🎉

The reason might be:

  [ 7] .rwtext           PROGBITS        40380000 0df000 000850 00  AX  0   0  4
  [ 8] .trap             PROGBITS        40380900 0df900 000c74 00  AX  0   0 256
  [ 9] .rwtext.wifi      PROGBITS        40381574 0e0574 002dfe 00  AX  0   0  2
  [10] .rwdata_dummy     NOBITS          3fc80000 0e4000 0042c2 00  AX  0   0  1
  [11] .data             PROGBITS        3fc842c8 0e42c8 001296 00  WA  0   0  8
  [12] .bss              NOBITS          3fc85560 0e5560 026b90 00  WA  0   0  8
  [13] .noinit           NOBITS          3fcac0f0 0e5560 000000 00  WA  0   0  4
  [14] .data.wifi        PROGBITS        3fcac0f0 0e60f0 000168 00  WA  0   0  4
  [15] .heap_start       NOBITS          3fcac258 0e6258 000000 00  WA  0   0  4

Here .trap ends up at 0x40380900 while .rwtext is just 0x850 sized. That's because of .balign 0x100 for the vector-table.
In .rwdata_dummy we just use SIZEOF to calculate the total size of .rwdata_dummy and so .data and .rwtext will overlap in SRAM.

Placing .trap first makes it match the alignment requirement without an additional gap

[bjoernQ]

we need this fix also for db-riscv-link.x and mb-riscv-link.x files

[MabezDev]

Nice find, that makes total sense! I've added the changes to the DB and MCUboot scripts.

[bjoernQ]

Thanks for fixing this