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Fix insertion location of trap section in ram #605

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Merged
MabezDev merged 3 commits into from
Jun 23, 2023
Merged

Fix insertion location of trap section in ram #605

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3d29557
Fix insertion location of trap section in ram
MabezDev Jun 21, 2023
05b396f
Apply fixes for db and mcuboot
MabezDev Jun 23, 2023
52683bb
Add changelog
MabezDev Jun 23, 2023
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2 changes: 1 addition & 1 deletion CHANGELOG.md
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Expand Up @@ -51,7 +51,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Fixed CI by pinning the log crate to 0.4.18 (#600)
- ESP32-S3: Fix calculation of PSRAM start address
- Fixed wrong variable access (FOSC CLK calibration for ESP32-C6 #593)

- Fixed [trap location in ram](https://github.com/esp-rs/esp-hal/pull/605#issuecomment-1604039683) (#605)
### Changed

- Improve examples documentation (#533)
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2 changes: 1 addition & 1 deletion esp32c2-hal/ld/bl-riscv-link.x
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Expand Up @@ -67,7 +67,7 @@ SECTIONS {
*(.trap.*);
} > RWTEXT
}
INSERT AFTER .rwtext;
INSERT BEFORE .rwtext;

SECTIONS {
/**
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4 changes: 2 additions & 2 deletions esp32c2-hal/ld/db-riscv-link.x
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Expand Up @@ -89,10 +89,10 @@ SECTIONS
_data_size = _data_end - _data_start + 8;
.rwtext ORIGIN(REGION_RWTEXT) + _data_size : AT(_text_size + _rodata_size + _data_size){
_srwtext = .;
*(.rwtext);
. = ALIGN(4);
KEEP(*(.trap));
*(.trap.*);
*(.rwtext);
. = ALIGN(4);
_erwtext = .;
} > REGION_RWTEXT
_rwtext_size = _erwtext - _srwtext + 8;
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2 changes: 1 addition & 1 deletion esp32c3-hal/ld/bl-riscv-link.x
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Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,7 @@ SECTIONS {
*(.trap.*);
} > RWTEXT
}
INSERT AFTER .rwtext;
INSERT BEFORE .rwtext;

SECTIONS {
/**
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4 changes: 2 additions & 2 deletions esp32c3-hal/ld/db-riscv-link.x
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Original file line number Diff line number Diff line change
Expand Up @@ -89,10 +89,10 @@ SECTIONS
_data_size = _data_end - _data_start + 8;
.rwtext ORIGIN(REGION_RWTEXT) + _data_size : AT(_text_size + _rodata_size + _data_size){
_srwtext = .;
*(.rwtext);
. = ALIGN(4);
KEEP(*(.trap));
*(.trap.*);
*(.rwtext);
. = ALIGN(4);
_erwtext = .;
} > REGION_RWTEXT
_rwtext_size = _erwtext - _srwtext + 8;
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2 changes: 1 addition & 1 deletion esp32c3-hal/ld/mb-riscv-link.x
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Expand Up @@ -64,9 +64,9 @@ SECTIONS
KEEP(*(.init));
KEEP(*(.init.rust));
KEEP(*(.text.abort));
. = ALIGN(4);
KEEP(*(.trap));
*(.trap.*);
. = ALIGN(4);

*libriscv-*.rlib:riscv.*(.literal .text .literal.* .text.*);
*libesp_riscv_rt-*.rlib:esp-riscv-rt.*(.literal .text .literal.* .text.*);
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2 changes: 1 addition & 1 deletion esp32c6-hal/ld/bl-riscv-link.x
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Original file line number Diff line number Diff line change
Expand Up @@ -71,7 +71,7 @@ SECTIONS {
*(.trap.*);
} > RWTEXT
}
INSERT AFTER .rwtext;
INSERT BEFORE .rwtext;

SECTIONS {
/**
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4 changes: 2 additions & 2 deletions esp32c6-hal/ld/db-riscv-link.x
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Original file line number Diff line number Diff line change
Expand Up @@ -94,10 +94,10 @@ SECTIONS
_data_size = _data_end - _data_start + 8;
.rwtext ORIGIN(REGION_RWTEXT) + _data_size : AT(_text_size + _rodata_size + _data_size){
_srwtext = .;
*(.rwtext);
. = ALIGN(4);
KEEP(*(.trap));
*(.trap.*);
*(.rwtext);
. = ALIGN(4);
_erwtext = .;
} > REGION_RWTEXT
_rwtext_size = _erwtext - _srwtext + 8;
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2 changes: 1 addition & 1 deletion esp32h2-hal/ld/bl-riscv-link.x
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,7 @@ SECTIONS {
*(.trap.*);
} > RWTEXT
}
INSERT AFTER .rwtext;
INSERT BEFORE .rwtext;

SECTIONS {
/**
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4 changes: 2 additions & 2 deletions esp32h2-hal/ld/db-riscv-link.x
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -94,10 +94,10 @@ SECTIONS
_data_size = _data_end - _data_start + 8;
.rwtext ORIGIN(REGION_RWTEXT) + _data_size : AT(_text_size + _rodata_size + _data_size){
_srwtext = .;
*(.rwtext);
. = ALIGN(4);
KEEP(*(.trap));
*(.trap.*);
*(.rwtext);
. = ALIGN(4);
_erwtext = .;
} > REGION_RWTEXT
_rwtext_size = _erwtext - _srwtext + 8;
Expand Down