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PR template related changes and The Big Warning Cleanup #666

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aca0c1d
Remove todo items checked by CI
bugadani Jul 20, 2023
9bf0748
Ensure warnings are not accepted
bugadani Jul 20, 2023
cddfeff
Resolve xtensa-specific warnings
bugadani Jul 20, 2023
7a73c52
Resolve riscv specific warnings
bugadani Jul 20, 2023
2d72178
Run checks in the specific directories
bugadani Jul 20, 2023
d0d5164
Check smartled crate with the correct targets
bugadani Jul 20, 2023
f8f16c4
Rustdoc improvements
bugadani Jul 20, 2023
37bf335
Format efuse bracketed names as code
bugadani Jul 20, 2023
471f7a7
Fix RMT spelling
bugadani Jul 20, 2023
f6ff5f1
Fix SPI docs
bugadani Jul 20, 2023
ebeddb6
Check interrupt_preemption examples with nightly
bugadani Jul 20, 2023
58933ff
Resolve example warnings
bugadani Jul 20, 2023
1a6e144
Work around warnings in riscv rt
bugadani Jul 20, 2023
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Resolve riscv specific warnings
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@bugadani
bugadani committed Jul 20, 2023
commit 7a73c52618a5e51c2ae77a7543ceff9333722fb6
35 changes: 21 additions & 14 deletions esp-hal-common/src/interrupt/riscv.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -510,7 +510,7 @@ pub fn _setup_interrupts() {
// at least after the 2nd stage bootloader there are some interrupts enabled
// (e.g. UART)
for peripheral_interrupt in 0..255 {
crate::soc::peripherals::Interrupt::try_from(peripheral_interrupt)
Interrupt::try_from(peripheral_interrupt)
.map(|intr| {
#[cfg(multi_core)]
disable(Cpu::AppCpu, intr);
Expand Down Expand Up @@ -548,16 +548,16 @@ pub fn disable(_core: Cpu, interrupt: Interrupt) {
pub fn get_status(_core: Cpu) -> u128 {
#[cfg(large_intr_status)]
unsafe {
((*crate::peripherals::INTERRUPT_CORE0::PTR)
((*peripherals::INTERRUPT_CORE0::PTR)
.intr_status_reg_0
.read()
.bits() as u128)
| ((*crate::peripherals::INTERRUPT_CORE0::PTR)
| ((*peripherals::INTERRUPT_CORE0::PTR)
.intr_status_reg_1
.read()
.bits() as u128)
<< 32
| ((*crate::peripherals::INTERRUPT_CORE0::PTR)
| ((*peripherals::INTERRUPT_CORE0::PTR)
.int_status_reg_2
.read()
.bits() as u128)
Expand All @@ -566,11 +566,11 @@ pub fn get_status(_core: Cpu) -> u128 {

#[cfg(not(large_intr_status))]
unsafe {
((*crate::peripherals::INTERRUPT_CORE0::PTR)
((*peripherals::INTERRUPT_CORE0::PTR)
.intr_status_reg_0
.read()
.bits() as u128)
| ((*crate::peripherals::INTERRUPT_CORE0::PTR)
| ((*peripherals::INTERRUPT_CORE0::PTR)
.intr_status_reg_1
.read()
.bits() as u128)
Expand All @@ -593,6 +593,7 @@ pub unsafe fn map(_core: Cpu, interrupt: Interrupt, which: CpuInterrupt) {

/// Get cpu interrupt assigned to peripheral interrupt
#[inline]
#[cfg(feature = "vectored")]
unsafe fn get_assigned_cpu_interrupt(interrupt: Interrupt) -> CpuInterrupt {
let interrupt_number = interrupt as isize;
let intr_map_base = crate::soc::registers::INTERRUPT_MAP_BASE as *mut u32;
Expand All @@ -605,18 +606,20 @@ unsafe fn get_assigned_cpu_interrupt(interrupt: Interrupt) -> CpuInterrupt {
#[cfg(not(plic))]
mod classic {
use super::{CpuInterrupt, InterruptKind, Priority};
use crate::Cpu;
use crate::{peripherals, Cpu};

#[cfg(feature = "vectored")]
pub(super) const PRIORITY_TO_INTERRUPT: [usize; 15] =
[1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15];

#[cfg(feature = "vectored")]
pub(super) const INTERRUPT_TO_PRIORITY: [usize; 15] =
[1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15];

/// Enable a CPU interrupt
pub unsafe fn enable_cpu_interrupt(which: CpuInterrupt) {
let cpu_interrupt_number = which as isize;
let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
let intr = &*peripherals::INTERRUPT_CORE0::PTR;
intr.cpu_int_enable
.modify(|r, w| w.bits((1 << cpu_interrupt_number) | r.bits()));
}
Expand All @@ -628,7 +631,7 @@ mod classic {
/// bits.
pub fn set_kind(_core: Cpu, which: CpuInterrupt, kind: InterruptKind) {
unsafe {
let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
let intr = &*peripherals::INTERRUPT_CORE0::PTR;
let cpu_interrupt_number = which as isize;

let interrupt_type = match kind {
Expand All @@ -650,7 +653,7 @@ mod classic {
/// default). Avoid changing the priority of interrupts 1 - 15 when
/// interrupt vectoring is enabled.
pub unsafe fn set_priority(_core: Cpu, which: CpuInterrupt, priority: Priority) {
let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
let intr = &*peripherals::INTERRUPT_CORE0::PTR;
let cpu_interrupt_number = which as isize;
let intr_prio_base = intr.cpu_int_pri_0.as_ptr();

Expand All @@ -664,16 +667,17 @@ mod classic {
pub fn clear(_core: Cpu, which: CpuInterrupt) {
unsafe {
let cpu_interrupt_number = which as isize;
let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
let intr = &*peripherals::INTERRUPT_CORE0::PTR;
intr.cpu_int_clear
.write(|w| w.bits(1 << cpu_interrupt_number));
}
}

/// Get interrupt priority
#[inline]
#[cfg(feature = "vectored")]
pub(super) unsafe fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority {
let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
let intr = &*peripherals::INTERRUPT_CORE0::PTR;
let intr_prio_base = intr.cpu_int_pri_0.as_ptr();

let prio = intr_prio_base
Expand All @@ -689,7 +693,7 @@ mod classic {
use super::mcause;
use crate::riscv;
let interrupt_id: usize = mcause::read().code(); // MSB is whether its exception or interrupt.
let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
let intr = &*peripherals::INTERRUPT_CORE0::PTR;
let interrupt_priority = intr
.cpu_int_pri_0
.as_ptr()
Expand All @@ -714,7 +718,7 @@ mod classic {
unsafe {
riscv::interrupt::disable();
}
let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
let intr = &*peripherals::INTERRUPT_CORE0::PTR;
intr.cpu_int_thresh.write(|w| w.bits(stored_prio));
}
}
Expand All @@ -727,9 +731,11 @@ mod plic {
// don't use interrupts reserved for CLIC (0,3,4,7)
// for some reason also CPU interrupt 8 doesn't work by default since it's
// disabled after reset - so don't use that, too
#[cfg(feature = "vectored")]
pub(super) const PRIORITY_TO_INTERRUPT: [usize; 15] =
[1, 2, 5, 6, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19];

#[cfg(feature = "vectored")]
pub(super) const INTERRUPT_TO_PRIORITY: [usize; 19] = [
1, 2, 0, 0, 3, 4, 0, 0, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
];
Expand Down Expand Up @@ -797,6 +803,7 @@ mod plic {

/// Get interrupt priority
#[inline]
#[cfg(feature = "vectored")]
pub(super) unsafe fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority {
let plic_mxint_pri_ptr = PLIC_MXINT0_PRI_REG as *mut u32;

Expand Down