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Merged
jessebraham merged 7 commits into from
Oct 11, 2023
Merged

Refactor the spi and spi_slave modules into a common spi module #843

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4440595
Refactor the `spi` and `spi_slave` modules into a single `spi` module
jessebraham Oct 11, 2023
88bea9a
Update import paths in examples as needed
jessebraham Oct 11, 2023
bc3a6d4
Extract some common types from `spi::master` into the root `spi` module
jessebraham Oct 11, 2023
239f8bf
Fix imports in examples (again)
jessebraham Oct 11, 2023
a222513
Documentation fixes/improvements
jessebraham Oct 11, 2023
905a962
Remove unnecessary re-exports
jessebraham Oct 11, 2023
aad8e97
Update `CHANGELOG.md`
jessebraham Oct 11, 2023
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Update CHANGELOG.md
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@jessebraham
jessebraham committed Oct 11, 2023
commit aad8e9759c5cd80984a7866a8bea3d56529e99ab
3 changes: 2 additions & 1 deletion CHANGELOG.md
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Expand Up @@ -26,7 +26,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Adding async support for RSA peripheral(doesn't work properly for `esp32` chip - issue will be created)(#790)
- Added sleep support for ESP32-C3 with timer and GPIO wakeups (#795)
- Support for ULP-RISCV including Delay and GPIO (#840)
- Add bare-bones SPI slave support, DMA only (#580)
- Add bare-bones SPI slave support, DMA only (#580, #843)
- Embassy `#[main]` convenience macro

### Changed
Expand Down Expand Up @@ -60,6 +60,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Unify the system peripheral, `SYSTEM`, `DPORT` and `PCR` are now all exposed as `SYSTEM` (#832).
- Unified the ESP32's and ESP32-C2's xtal frequency features (#831)
- Replace any underscores in feature names with dashes (#833)
- The `spi` and `spi_slave` modules have been refactored into the `spi`, `spi::master`, and `spi::slave` modules (#843)

## [0.12.0]

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