Include assertions.svh header in all sources using assertions

Partially reproducible with the following sed command:
sed -zi 's/\nmodule/\n`include "common_cells\/assertions.svh"\n\nmodule/g' `grep assert src/*.sv`

Requires extensive cleanup.

src/addr_decode_dync.sv

@@ -14,6 +14,8 @@
 // - Michael Rogenmoser <[email protected]>
 // - Thomas Benz <[email protected]>
 
+`include "common_cells/assertions.svh"
+
 /// Address Decoder: Maps the input address combinatorially to an index.
 /// DYNamic Configuration (DYNC) version
 /// The address map `addr_map_i` is a packed array of rule_t structs.

src/cb_filter.sv

@@ -39,6 +39,8 @@
 //   - `filter_empty_o`:  Filter is empty.
 //   - `filter_error_o`:  One of the internal counters or buckets overflowed.
 
+`include "common_cells/assertions.svh"
+
 /// This is a counting bloom filter
 module cb_filter #(
   parameter int unsigned KHashes     =  32'd3,  // Number of hash functions

src/cdc_2phase_clearable.sv

@@ -49,6 +49,7 @@
 /* verilator lint_off DECLFILENAME */
 
 `include "common_cells/registers.svh"
+`include "common_cells/assertions.svh"
 
 module cdc_2phase_clearable #(
   parameter type T = logic,

src/cdc_fifo_2phase.sv

@@ -11,6 +11,8 @@
 //
 // Fabian Schuiki <[email protected]>
 
+`include "common_cells/assertions.svh"
+
 /// A clock domain crossing FIFO, using 2-phase hand shakes.
 ///
 /// This FIFO has its push and pop ports in two separate clock domains. Its size

src/cdc_fifo_gray.sv

@@ -96,6 +96,7 @@
 /// ```
 
 `include "common_cells/registers.svh"
+`include "common_cells/assertions.svh"
 
 (* no_ungroup *)
 (* no_boundary_optimization *)

src/cdc_fifo_gray_clearable.sv

@@ -96,6 +96,7 @@
 /// async] ```
 
 `include "common_cells/registers.svh"
+`include "common_cells/assertions.svh"
 
 (* no_ungroup *)
 (* no_boundary_optimization *)

src/exp_backoff.sv

@@ -20,6 +20,8 @@
 // a successful trial (clr_i).
 //
 
+`include "common_cells/assertions.svh"
+
 module exp_backoff #(
   /// Seed for 16bit LFSR
   parameter int unsigned Seed   = 'hffff,

src/fifo_v3.sv

@@ -10,6 +10,8 @@
 
 // Author: Florian Zaruba <[email protected]>
 
+`include "common_cells/assertions.svh"
+
 module fifo_v3 #(
     parameter bit          FALL_THROUGH = 1'b0, // fifo is in fall-through mode
     parameter int unsigned DATA_WIDTH   = 32,   // default data width if the fifo is of type logic

src/id_queue.sv

@@ -45,6 +45,8 @@
 // Maintainers:
 // - Andreas Kurth <[email protected]>
 
+`include "common_cells/assertions.svh"
+
 module id_queue #(
     parameter int ID_WIDTH  = 0,
     parameter int CAPACITY  = 0,

src/isochronous_4phase_handshake.sv

@@ -39,6 +39,7 @@
 /// ratio will work.
 
 `include "common_cells/registers.svh"
+`include "common_cells/assertions.svh"
 
 module isochronous_4phase_handshake (
   input  logic src_clk_i,

src/isochronous_spill_register.sv

@@ -12,6 +12,7 @@
 // Florian Zaruba <[email protected]>
 
 `include "common_cells/registers.svh"
+`include "common_cells/assertions.svh"
 
 /// A register with handshakes that completely cuts any combinatorial paths
 /// between the input and output in isochronous clock domains.

src/lfsr.sv

@@ -19,6 +19,8 @@
 // patterns. The additional cipher layers can only be used for an LFSR width
 // of 64bit, since the block cipher has been designed for that block length.
 
+`include "common_cells/assertions.svh"
+
 module lfsr #(
   parameter int unsigned          LfsrWidth     = 64,   // [4,64]
   parameter int unsigned          OutWidth      = 8,    // [1,LfsrWidth]

src/lfsr_16bit.sv

@@ -12,6 +12,8 @@
 // Date: 5.11.2018
 // Description: 16-bit LFSR
 
+`include "common_cells/assertions.svh"
+
 // --------------
 // 16-bit LFSR
 // --------------

src/lfsr_8bit.sv

@@ -13,6 +13,8 @@
 // Date: 12.11.2017
 // Description: 8-bit LFSR
 
+`include "common_cells/assertions.svh"
+
 /// 8 bit Linear Feedback Shift register
 module lfsr_8bit #(
   parameter logic        [7:0] SEED  = 8'b0,

src/lzc.sv

@@ -2,6 +2,8 @@
 // Solderpad Hardware License, Version 0.51, see LICENSE for details.
 // SPDX-License-Identifier: SHL-0.51
 
+`include "common_cells/assertions.svh"
+
 /// A trailing zero counter / leading zero counter.
 /// Set MODE to 0 for trailing zero counter => cnt_o is the number of trailing zeros (from the LSB)
 /// Set MODE to 1 for leading zero counter  => cnt_o is the number of leading zeros  (from the MSB)

src/mem_to_banks_detailed.sv

@@ -10,6 +10,8 @@
 //
 // Author: Wolfgang Roenninger <[email protected]>
 
+`include "common_cells/assertions.svh"
+
 /// Split memory access over multiple parallel banks, where each bank has its own req/gnt
 /// request and valid response direction.
 module mem_to_banks_detailed #(

src/multiaddr_decode.sv

@@ -10,6 +10,8 @@
 
 // Author: Luca Colagrande <[email protected]>
 
+`include "common_cells/assertions.svh"
+
 /// Multi-address Decoder: Combinational module which takes an address set
 /// in {addr, mask} representation and returns a bit mask `select_o` indicating which
 /// address map rules in `addr_map_i` it matches.

src/onehot_to_bin.sv

@@ -10,6 +10,8 @@
 
 // Franceco Conti <[email protected]>
 
+`include "common_cells/assertions.svh"
+
 module onehot_to_bin #(
     parameter int unsigned ONEHOT_WIDTH = 16,
     // Do Not Change

src/plru_tree.sv

@@ -14,6 +14,8 @@
 // Description: Pseudo Least Recently Used Tree (PLRU)
 // See: https://en.wikipedia.org/wiki/Pseudo-LRU
 
+`include "common_cells/assertions.svh"
+
 module plru_tree #(
   parameter int unsigned ENTRIES = 16
 ) (

src/rr_arb_tree.sv

@@ -13,6 +13,8 @@
 // Date: 02.04.2019
 // Description: logarithmic arbitration tree with round robin arbitration scheme.
 
+`include "common_cells/assertions.svh"
+
 /// The rr_arb_tree employs non-starving round robin-arbitration - i.e., the priorities
 /// rotate each cycle.
 ///

src/spill_register_flushable.sv

@@ -11,6 +11,7 @@
 //
 // Fabian Schuiki <[email protected]>
 
+`include "common_cells/assertions.svh"
 
 /// A register with handshakes that completely cuts any combinational paths
 /// between the input and output. This spill register can be flushed.

src/stream_fork.sv

@@ -16,6 +16,8 @@
 // This module has no data ports because stream data does not need to be forked: the data of the
 // input stream can just be applied at all output streams.
 
+`include "common_cells/assertions.svh"
+
 module stream_fork #(
     parameter int unsigned N_OUP = 0    // Synopsys DC requires a default value for parameters.
 ) (

src/stream_fork_dynamic.sv

@@ -11,6 +11,8 @@
 // Authors:
 // - Andreas Kurth <[email protected]>
 
+`include "common_cells/assertions.svh"
+
 /// Dynamic stream fork: Connects the input stream (ready-valid) handshake to a combination of output
 /// stream handshake.  The combination is determined dynamically through another stream, which
 /// provides a bitmask for the fork.  For each input stream handshake, every output stream handshakes

src/stream_join_dynamic.sv

@@ -11,6 +11,8 @@
 // Authors:
 // - Luca Colagrande <[email protected]>
 
+`include "common_cells/assertions.svh"
+
 // Stream join dynamic: Joins a parametrizable number of input streams (i.e. valid-ready
 // handshaking with dependency rules as in AXI4) to a single output stream. The subset of streams
 // to join can be configured dynamically via `sel_i`. The output handshake happens only after

src/stream_mux.sv

@@ -8,6 +8,8 @@
 // CONDITIONS OF ANY KIND, either express or implied. See the License for the
 // specific language governing permissions and limitations under the License.
 
+`include "common_cells/assertions.svh"
+
 /// Stream multiplexer: connects the output to one of `N_INP` data streams with valid-ready
 /// handshaking.
 

src/stream_omega_net.sv

@@ -10,6 +10,8 @@
 
 // Author: Wolfgang Roenninger <[email protected]>
 
+`include "common_cells/assertions.svh"
+
 /// Omega network using multiple `stream_xbar` as switches.
 ///
 /// An omega network is isomorphic to a butterfly network.

src/stream_to_mem.sv

@@ -11,9 +11,11 @@
 // Authors:
 // - Andreas Kurth <[email protected]>
 
+`include "common_cells/registers.svh"
+`include "common_cells/assertions.svh"
+
 /// `stream_to_mem`: Allows to use memories with flow control (`valid`/`ready`) for requests but without flow
 /// control for output data to be used in streams.
-`include "common_cells/registers.svh"
 module stream_to_mem #(
   /// Memory request payload type, usually write enable, write data, etc.
   parameter type         mem_req_t  = logic,

src/stream_xbar.sv

@@ -10,6 +10,8 @@
 
 // Author: Wolfgang Roenninger <[email protected]>
 
+`include "common_cells/assertions.svh"
+
 /// Fully connected stream crossbar.
 ///
 /// Handshaking rules as defined by the `AMBA AXI` standard on default.