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Promote armv8r-none-eabihf target to Tier 2 #146520
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Some changes occurred in src/doc/rustc/src/platform-support cc @Noratrieb |
rustbot has assigned @petrochenkov. Use |
This is the target for supporting Arm Cortex-R52 bare-metal systems, which are common in safety-critical systems.
Rebased now #146419 is in. |
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These commits modify compiler targets. |
This PR was rebased onto a different master commit. Here's a range-diff highlighting what actually changed. Rebasing is a normal part of keeping PRs up to date, so no action is needed—this note is just to help reviewers. |
Blocked on rust-lang/compiler-team#914. |
… r=jackh726 Demote both armebv7r-none-* targets. OK, slightly more controversial than rust-lang#146520 and rust-lang#146522 - I'd like to drop the bare-metal **big-endian** Armv7-R targets down to Tier 3. The reason is simple - we cannot test them in https://github.com/rust-embedded/cortex-ar/. This because QEMU support for Big Endian Armv7-R is broken. I tried quite hard, but all the strings I printed with semihosting came out byte swapped (or "etybawa depp") because of how QEMU kludges the access to memory in big-endian mode. The target also has only a single maintainer. Although, if `@chrisnc` wants to put up a case for keeping it at Tier 2 though, I'm happy to hear it! This PR wil be rebased once rust-lang#146419 completes the queue.
… r=jackh726 Demote both armebv7r-none-* targets. OK, slightly more controversial than rust-lang#146520 and rust-lang#146522 - I'd like to drop the bare-metal **big-endian** Armv7-R targets down to Tier 3. The reason is simple - we cannot test them in https://github.com/rust-embedded/cortex-ar/. This because QEMU support for Big Endian Armv7-R is broken. I tried quite hard, but all the strings I printed with semihosting came out byte swapped (or "etybawa depp") because of how QEMU kludges the access to memory in big-endian mode. The target also has only a single maintainer. Although, if ``@chrisnc`` wants to put up a case for keeping it at Tier 2 though, I'm happy to hear it! This PR wil be rebased once rust-lang#146419 completes the queue.
… r=jackh726 Demote both armebv7r-none-* targets. OK, slightly more controversial than rust-lang#146520 and rust-lang#146522 - I'd like to drop the bare-metal **big-endian** Armv7-R targets down to Tier 3. The reason is simple - we cannot test them in https://github.com/rust-embedded/cortex-ar/. This because QEMU support for Big Endian Armv7-R is broken. I tried quite hard, but all the strings I printed with semihosting came out byte swapped (or "etybawa depp") because of how QEMU kludges the access to memory in big-endian mode. The target also has only a single maintainer. Although, if ```@chrisnc``` wants to put up a case for keeping it at Tier 2 though, I'm happy to hear it! This PR wil be rebased once rust-lang#146419 completes the queue.
… r=jackh726 Demote both armebv7r-none-* targets. OK, slightly more controversial than rust-lang#146520 and rust-lang#146522 - I'd like to drop the bare-metal **big-endian** Armv7-R targets down to Tier 3. The reason is simple - we cannot test them in https://github.com/rust-embedded/cortex-ar/. This because QEMU support for Big Endian Armv7-R is broken. I tried quite hard, but all the strings I printed with semihosting came out byte swapped (or "etybawa depp") because of how QEMU kludges the access to memory in big-endian mode. The target also has only a single maintainer. Although, if ````@chrisnc```` wants to put up a case for keeping it at Tier 2 though, I'm happy to hear it! This PR wil be rebased once rust-lang#146419 completes the queue.
Rollup merge of #146523 - thejpster:demote-armebv7r-targets, r=jackh726 Demote both armebv7r-none-* targets. OK, slightly more controversial than #146520 and #146522 - I'd like to drop the bare-metal **big-endian** Armv7-R targets down to Tier 3. The reason is simple - we cannot test them in https://github.com/rust-embedded/cortex-ar/. This because QEMU support for Big Endian Armv7-R is broken. I tried quite hard, but all the strings I printed with semihosting came out byte swapped (or "etybawa depp") because of how QEMU kludges the access to memory in big-endian mode. The target also has only a single maintainer. Although, if ````@chrisnc```` wants to put up a case for keeping it at Tier 2 though, I'm happy to hear it! This PR wil be rebased once #146419 completes the queue.
Demote both armebv7r-none-* targets. OK, slightly more controversial than rust-lang/rust#146520 and rust-lang/rust#146522 - I'd like to drop the bare-metal **big-endian** Armv7-R targets down to Tier 3. The reason is simple - we cannot test them in https://github.com/rust-embedded/cortex-ar/. This because QEMU support for Big Endian Armv7-R is broken. I tried quite hard, but all the strings I printed with semihosting came out byte swapped (or "etybawa depp") because of how QEMU kludges the access to memory in big-endian mode. The target also has only a single maintainer. Although, if ````@chrisnc```` wants to put up a case for keeping it at Tier 2 though, I'm happy to hear it! This PR wil be rebased once rust-lang/rust#146419 completes the queue.
This PR promotes armv8r-none-eabihf to Tier 2, joining armv7r-none-eabi, armv7r-none-eabihf and armv7a-none-eabi.
This PR wil be rebased once #146419 completes the queue.
The
armv8r-none-eabihf
target is for the Arm Cortex-R52 processor, as found in a number of Automotive SoCs that have just been released, or are about to be released. Currently SoCs are available from NXP and Renesas.The Embedded Devices Working Group's Arm Team have just started maintaining this target.
This target is highly similar to a number of existing Tier 2 targets, including
armv7r-none-eabihf
and so it should not add undue burden.https://doc.rust-lang.org/nightly/rustc/platform-support/armv8r-none-eabihf.html exists and was updated in #146419
I believe it does.
The Armv8-R architecture introduces a new FPU type, the fp-armv8, and so this requires a unique target.
It has a full libcore, as per the other arm*-none-* targets.
It should be the same backend as
armv7r-none-eabihf
and friends, except for FPU support, which is already covered inthumbv8m.main-none-eabihf
. There are no issues that I know of.The ABI is EABI, the same as many other Arm targets.
The https://github.com/rust-embedded/cortex-ar repository regularly builds this target with
-Zbuild-std=core
and it seems fine.There are no no-std tests in the tree that I'm aware of.
Building libcore is quite fast.
It does.
Just libcore required (and liballoc). No known issues here.
Noted
The https://github.com/rust-embedded/cortex-ar repository will be changed to use the rustup component when available.
Noted