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This PR promotes armv8r-none-eabihf to Tier 2, joining armv7r-none-eabi, armv7r-none-eabihf and armv7a-none-eabi.

This PR wil be rebased once #146419 completes the queue.

  • A tier 2 target must have value to people other than its maintainers. (It may
    still be a niche target, but it must not be exclusively useful for an
    inherently closed group.)

The armv8r-none-eabihf target is for the Arm Cortex-R52 processor, as found in a number of Automotive SoCs that have just been released, or are about to be released. Currently SoCs are available from NXP and Renesas.

  • A tier 2 target must have a designated team of developers (the "target
    maintainers") available to consult on target-specific build-breaking issues,
    or if necessary to develop target-specific language or library implementation
    details. This team must have at least 2 developers.

The Embedded Devices Working Group's Arm Team have just started maintaining this target.

  • The target must not place undue burden on Rust developers not specifically
    concerned with that target. Rust developers are expected to not gratuitously
    break a tier 2 target, but are not expected to become experts in every tier 2
    target, and are not expected to provide target-specific implementations for
    every tier 2 target.

This target is highly similar to a number of existing Tier 2 targets, including armv7r-none-eabihf and so it should not add undue burden.

  • The target must provide documentation for the Rust community explaining how
    to build for the target using cross-compilation, and explaining how to run
    tests for the target. If at all possible, this documentation should show how
    to run Rust programs and tests for the target using emulation, to allow
    anyone to do so. If the target cannot be feasibly emulated, the documentation
    should explain how to obtain and work with physical hardware, cloud systems,
    or equivalent.

https://doc.rust-lang.org/nightly/rustc/platform-support/armv8r-none-eabihf.html exists and was updated in #146419

  • The target must document its baseline expectations for the features or
    versions of CPUs, operating systems, libraries, runtime environments, and
    similar.

I believe it does.

  • If introducing a new tier 2 or higher target that is identical to an existing
    Rust target except for the baseline expectations for the features or versions
    of CPUs, operating systems, libraries, runtime environments, and similar,
    then the proposed target must document to the satisfaction of the approving
    teams why the specific difference in baseline expectations provides
    sufficient value to justify a separate target.

The Armv8-R architecture introduces a new FPU type, the fp-armv8, and so this requires a unique target.

  • Tier 2 targets must not leave any significant portions of core or the
    standard library unimplemented or stubbed out, unless they cannot possibly be
    supported on the target.

It has a full libcore, as per the other arm*-none-* targets.

  • The code generation backend for the target should not have deficiencies that
    invalidate Rust safety properties, as evaluated by the Rust compiler team.

It should be the same backend as armv7r-none-eabihf and friends, except for FPU support, which is already covered in thumbv8m.main-none-eabihf. There are no issues that I know of.

  • If the target supports C code, and the target has an interoperable calling
    convention for C code, the Rust target must support that C calling convention
    for the platform via extern "C". The C calling convention does not need to
    be the default Rust calling convention for the target, however.

The ABI is EABI, the same as many other Arm targets.

  • The target must build reliably in CI, for all components that Rust's CI
    considers mandatory.

The https://github.com/rust-embedded/cortex-ar repository regularly builds this target with -Zbuild-std=core and it seems fine.

  • The approving teams may additionally require that a subset of tests pass in
    CI, such as enough to build a functional "hello world" program, ./x.py test --no-run, or equivalent "smoke tests". In particular, this requirement may
    apply if the target builds host tools, or if the tests in question provide
    substantial value via early detection of critical problems.

There are no no-std tests in the tree that I'm aware of.

  • Building the target in CI must not take substantially longer than the current
    slowest target in CI, and should not substantially raise the maintenance
    burden of the CI infrastructure. This requirement is subjective, to be
    evaluated by the infrastructure team, and will take the community importance
    of the target into account.

Building libcore is quite fast.

  • Tier 2 targets should, if at all possible, support cross-compiling. Tier 2
    targets should not require using the target as the host for builds, even if
    the target supports host tools.

It does.

  • In addition to the legal requirements for all targets (specified in the tier
    3 requirements), because a tier 2 target typically involves the Rust project
    building and supplying various compiled binaries, incorporating the target
    and redistributing any resulting compiled binaries (e.g. built libraries,
    host tools if any) must not impose any onerous license requirements on any
    members of the Rust project, including infrastructure team members and those
    operating CI systems. This is a subjective requirement, to be evaluated by
    the approving teams.

Just libcore required (and liballoc). No known issues here.

  • Tier 2 targets must not impose burden on the authors of pull requests, or
    other developers in the community, to ensure that tests pass for the target.

Noted

  • The target maintainers should regularly run the testsuite for the target

The https://github.com/rust-embedded/cortex-ar repository will be changed to use the rustup component when available.

and should fix any test failures in a reasonably timely fashion.

Noted

@rustbot rustbot added the S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. label Sep 13, 2025
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rustbot commented Sep 13, 2025

Some changes occurred in src/doc/rustc/src/platform-support

cc @Noratrieb

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rustbot commented Sep 13, 2025

r? @petrochenkov

rustbot has assigned @petrochenkov.
They will have a look at your PR within the next two weeks and either review your PR or reassign to another reviewer.

Use r? to explicitly pick a reviewer

This is the target for supporting Arm Cortex-R52 bare-metal systems,
which are common in safety-critical systems.
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Rebased now #146419 is in.

@thejpster thejpster force-pushed the promote-armv8r-none-eabi branch from 90f0baa to bfddf29 Compare September 14, 2025 08:53
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rustbot commented Sep 14, 2025

These commits modify compiler targets.
(See the Target Tier Policy.)

@rustbot rustbot added the T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. label Sep 14, 2025
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rustbot commented Sep 14, 2025

This PR was rebased onto a different master commit. Here's a range-diff highlighting what actually changed.

Rebasing is a normal part of keeping PRs up to date, so no action is needed—this note is just to help reviewers.

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Blocked on rust-lang/compiler-team#914.
@rustbot blocked

@rustbot rustbot added S-blocked Status: Blocked on something else such as an RFC or other implementation work. and removed S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Sep 24, 2025
matthiaskrgr added a commit to matthiaskrgr/rust that referenced this pull request Sep 26, 2025
… r=jackh726

Demote both armebv7r-none-* targets.

OK, slightly more controversial than rust-lang#146520 and rust-lang#146522  - I'd like to drop the bare-metal **big-endian** Armv7-R targets down to Tier 3.

The reason is simple - we cannot test them in https://github.com/rust-embedded/cortex-ar/. This because QEMU support for Big Endian Armv7-R is broken. I tried quite hard, but all the strings I printed with semihosting came out byte swapped (or "etybawa depp") because of how QEMU kludges the access to memory in big-endian mode.

The target also has only a single maintainer. Although, if `@chrisnc` wants to put up a case for keeping it at Tier 2 though, I'm happy to hear it!

This PR wil be rebased once rust-lang#146419 completes the queue.
matthiaskrgr added a commit to matthiaskrgr/rust that referenced this pull request Sep 26, 2025
… r=jackh726

Demote both armebv7r-none-* targets.

OK, slightly more controversial than rust-lang#146520 and rust-lang#146522  - I'd like to drop the bare-metal **big-endian** Armv7-R targets down to Tier 3.

The reason is simple - we cannot test them in https://github.com/rust-embedded/cortex-ar/. This because QEMU support for Big Endian Armv7-R is broken. I tried quite hard, but all the strings I printed with semihosting came out byte swapped (or "etybawa depp") because of how QEMU kludges the access to memory in big-endian mode.

The target also has only a single maintainer. Although, if ``@chrisnc`` wants to put up a case for keeping it at Tier 2 though, I'm happy to hear it!

This PR wil be rebased once rust-lang#146419 completes the queue.
matthiaskrgr added a commit to matthiaskrgr/rust that referenced this pull request Sep 26, 2025
… r=jackh726

Demote both armebv7r-none-* targets.

OK, slightly more controversial than rust-lang#146520 and rust-lang#146522  - I'd like to drop the bare-metal **big-endian** Armv7-R targets down to Tier 3.

The reason is simple - we cannot test them in https://github.com/rust-embedded/cortex-ar/. This because QEMU support for Big Endian Armv7-R is broken. I tried quite hard, but all the strings I printed with semihosting came out byte swapped (or "etybawa depp") because of how QEMU kludges the access to memory in big-endian mode.

The target also has only a single maintainer. Although, if ```@chrisnc``` wants to put up a case for keeping it at Tier 2 though, I'm happy to hear it!

This PR wil be rebased once rust-lang#146419 completes the queue.
matthiaskrgr added a commit to matthiaskrgr/rust that referenced this pull request Sep 26, 2025
… r=jackh726

Demote both armebv7r-none-* targets.

OK, slightly more controversial than rust-lang#146520 and rust-lang#146522  - I'd like to drop the bare-metal **big-endian** Armv7-R targets down to Tier 3.

The reason is simple - we cannot test them in https://github.com/rust-embedded/cortex-ar/. This because QEMU support for Big Endian Armv7-R is broken. I tried quite hard, but all the strings I printed with semihosting came out byte swapped (or "etybawa depp") because of how QEMU kludges the access to memory in big-endian mode.

The target also has only a single maintainer. Although, if ````@chrisnc```` wants to put up a case for keeping it at Tier 2 though, I'm happy to hear it!

This PR wil be rebased once rust-lang#146419 completes the queue.
rust-timer added a commit that referenced this pull request Sep 27, 2025
Rollup merge of #146523 - thejpster:demote-armebv7r-targets, r=jackh726

Demote both armebv7r-none-* targets.

OK, slightly more controversial than #146520 and #146522  - I'd like to drop the bare-metal **big-endian** Armv7-R targets down to Tier 3.

The reason is simple - we cannot test them in https://github.com/rust-embedded/cortex-ar/. This because QEMU support for Big Endian Armv7-R is broken. I tried quite hard, but all the strings I printed with semihosting came out byte swapped (or "etybawa depp") because of how QEMU kludges the access to memory in big-endian mode.

The target also has only a single maintainer. Although, if ````@chrisnc```` wants to put up a case for keeping it at Tier 2 though, I'm happy to hear it!

This PR wil be rebased once #146419 completes the queue.
github-actions bot pushed a commit to rust-lang/rust-analyzer that referenced this pull request Sep 29, 2025
Demote both armebv7r-none-* targets.

OK, slightly more controversial than rust-lang/rust#146520 and rust-lang/rust#146522  - I'd like to drop the bare-metal **big-endian** Armv7-R targets down to Tier 3.

The reason is simple - we cannot test them in https://github.com/rust-embedded/cortex-ar/. This because QEMU support for Big Endian Armv7-R is broken. I tried quite hard, but all the strings I printed with semihosting came out byte swapped (or "etybawa depp") because of how QEMU kludges the access to memory in big-endian mode.

The target also has only a single maintainer. Although, if ````@chrisnc```` wants to put up a case for keeping it at Tier 2 though, I'm happy to hear it!

This PR wil be rebased once rust-lang/rust#146419 completes the queue.
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