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[RISC-V] Implement On Stack Replacement #1

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Merged
sirntar merged 31 commits into from
Dec 7, 2023
Merged

[RISC-V] Implement On Stack Replacement #1

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2803037
[RISC-V] Set OSR root frames reg for large offset
sirntar Nov 28, 2023
4eaddc1
[RISC-V] Enable OSR feature in cmake
sirntar Nov 28, 2023
bff6fe5
[RISC-V] Add config info about QuickJitForLoops
sirntar Nov 28, 2023
43b5a49
[RISC-V] Add osr ifdef directives to codegencommon
sirntar Nov 28, 2023
42c1b20
[RISC-V] Redesign FuncletFrameInfoDsc for OSR
sirntar Nov 29, 2023
c32d8a8
[RISC-V] Correct some assembly comments
sirntar Nov 29, 2023
fbd338a
[RISC-V] Rebuild genFuncletProlog for OSR
sirntar Nov 30, 2023
405bdab
[RISC-V] Add some documentation in coments
sirntar Dec 1, 2023
d2fb93b
[RISC-V] Fix potential issue for 0 calee-save regs
sirntar Dec 1, 2023
b799803
[RISC-V] Rebuild OSR epilog
sirntar Dec 1, 2023
53a6dc1
[RISC-V] Rebuild genCaptureFuncletPrologEpilogInfo for OSR
sirntar Dec 1, 2023
b306acb
[RISC-V] Add OSR support in genSetPSPSym
sirntar Dec 1, 2023
9ad6889
[RISC-V] Cosmetic changes in genSetRegToConst
sirntar Dec 1, 2023
3ad737d
[RISC-V] Add coment to genCodeForCpObj
sirntar Dec 1, 2023
f05be9c
[RISC-V] Cleanup in genCodeForCompare for OSR
sirntar Dec 1, 2023
1e13920
[RISC-V] Improve some SP/FP delta manimulations
sirntar Dec 1, 2023
058aadc
[RISC-V] Add OSR support to genSetGSSecurityCookie
sirntar Dec 1, 2023
4e0823e
[RISC-V] Implement genPushCalleeSavedRegisters for OSR
sirntar Dec 4, 2023
65324eb
[RISC-V] Implement genPopCalleeSavedRegisters for OSR
sirntar Dec 5, 2023
e2d6fd9
[RISC-V] Update vars for OSR in Compiler
sirntar Dec 5, 2023
05b50f2
[RISC-V] Update gcInfoBlockHdrSave for OSR
sirntar Dec 5, 2023
cba3bf6
[RISC-V] Enable TC_OnStackReplacement
sirntar Dec 5, 2023
9079076
[RISC-V] Correct compiler OSR vars
sirntar Dec 5, 2023
a940ddd
[RISC-V] Fix codegen definition
sirntar Dec 5, 2023
bf3dca9
[RISC-V] Correct spelling of SPtoCallerSPdelta
sirntar Dec 5, 2023
1c002d4
[RISC-V] Add missing semicolon
sirntar Dec 5, 2023
99a5d05
[RISC-V] Fix IsOSR is not a pointer member
sirntar Dec 5, 2023
5423fa9
[RISC-V] Fix OSR errors
sirntar Dec 5, 2023
1092662
[RISC-V] A little correction and cleanup
sirntar Dec 6, 2023
d6d8f4c
[RISC-V] Add some docs and small optimization changes
sirntar Dec 7, 2023
e6116dc
[RISC-V] Remove space before genCaptureFuncletPrologEpilogInfo
sirntar Dec 7, 2023
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[RISC-V] Correct compiler OSR vars
  • Loading branch information
@sirntar
sirntar committed Dec 5, 2023
commit 9079076710a72d9b9f402f4bf2bc0a862a3f72eb
33 changes: 11 additions & 22 deletions src/coreclr/jit/lclvars.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5229,7 +5229,7 @@ void Compiler::lvaFixVirtualFrameOffsets()

if (opts.IsOSR())
{
#if defined(TARGET_AMD64) || defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64)
#if defined(TARGET_AMD64) || defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
// Stack offset includes Tier0 frame.
//
JITDUMP("--- delta bump %d for OSR + Tier0 frame\n", info.compPatchpointInfo->TotalFrameSize());
Expand Down Expand Up @@ -5334,7 +5334,7 @@ void Compiler::lvaFixVirtualFrameOffsets()

#endif // FEATURE_FIXED_OUT_ARGS

#if defined(TARGET_ARM64) || defined(TARGET_RISCV64)
#if defined(TARGET_ARM64)
// We normally add alignment below the locals between them and the outgoing
// arg space area. When we store fp/lr(ra) at the bottom, however, this will
// be below the alignment. So we should not apply the alignment adjustment to
Expand All @@ -5346,11 +5346,11 @@ void Compiler::lvaFixVirtualFrameOffsets()
{
lvaTable[lvaRetAddrVar].SetStackOffset(REGSIZE_BYTES);
}
#elif defined(TARGET_LOONGARCH64)
#elif defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
assert(codeGen->isFramePointerUsed());
if (lvaRetAddrVar != BAD_VAR_NUM)
{
// For LoongArch64, the RA is below the fp. see the `genPushCalleeSavedRegisters`
// For LoongArch64 and RISCV64, the RA is below the fp. see the `genPushCalleeSavedRegisters`
lvaTable[lvaRetAddrVar].SetStackOffset(-REGSIZE_BYTES);
}
#endif // !TARGET_LOONGARCH64
Expand Down Expand Up @@ -6139,17 +6139,11 @@ void Compiler::lvaAssignVirtualFrameOffsetsToLocals()
stkOffs -= (compCalleeRegsPushed - 2) * REGSIZE_BYTES;
}

#elif defined(TARGET_LOONGARCH64)

assert(compCalleeRegsPushed >= 2);

#elif defined(TARGET_RISCV64)
#elif defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)

// Subtract off FP and RA.
assert(compCalleeRegsPushed >= 2);
stkOffs -= (compCalleeRegsPushed - 2) * REGSIZE_BYTES;

#else // !TARGET_RISCV64
#else // !TARGET_LOONGARCH64 && !TARGET_RISCV64
#ifdef TARGET_ARM
// On ARM32 LR is part of the pushed registers and is always stored at the
// top.
Expand All @@ -6160,7 +6154,7 @@ void Compiler::lvaAssignVirtualFrameOffsetsToLocals()
#endif

stkOffs -= compCalleeRegsPushed * REGSIZE_BYTES;
#endif // !TARGET_RISCV64
#endif // !TARGET_LOONGARCH64 && !TARGET_RISCV64

// (2) Account for the remainder of the frame
//
Expand Down Expand Up @@ -6882,11 +6876,6 @@ void Compiler::lvaAssignVirtualFrameOffsetsToLocals()
}
#endif // TARGET_ARM64

#if defined(TARGET_RISCV64)
assert(isFramePointerUsed()); // Note that currently we always have a frame pointer
stkOffs -= 2 * REGSIZE_BYTES;
#endif // TARGET_RISCV64

#if FEATURE_FIXED_OUT_ARGS
if (lvaOutgoingArgSpaceSize > 0)
{
Expand All @@ -6903,8 +6892,8 @@ void Compiler::lvaAssignVirtualFrameOffsetsToLocals()
}
#endif // FEATURE_FIXED_OUT_ARGS

#ifdef TARGET_LOONGARCH64
// For LoongArch64, CalleeSavedRegs are at bottom.
#if defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
// For LoongArch64 and RISCV64, CalleeSavedRegs are at bottom.
int pushedCount = 0;
#else
// compLclFrameSize equals our negated virtual stack offset minus the pushed registers and return address
Expand Down Expand Up @@ -7891,7 +7880,7 @@ int Compiler::lvaToCallerSPRelativeOffset(int offset, bool isFpBased, bool forRo
offset += codeGen->genCallerSPtoInitialSPdelta();
}

#if defined(TARGET_AMD64) || defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64)
#if defined(TARGET_AMD64) || defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
if (forRootFrame && opts.IsOSR())
{
const PatchpointInfo* const ppInfo = info.compPatchpointInfo;
Expand All @@ -7910,7 +7899,7 @@ int Compiler::lvaToCallerSPRelativeOffset(int offset, bool isFpBased, bool forRo
//
const int adjustment = ppInfo->TotalFrameSize() + REGSIZE_BYTES;

#elif defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64)
#elif defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)

const int adjustment = ppInfo->TotalFrameSize();
#endif
Expand Down