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bd0d9a6
sys: bump capstone to 6.0.0-alpha4, fix arm64 and sysz rename
jiegec May 23, 2025
e794cd0
rs: rename arm64 -> aarch64 and sysz -> systemz to follow upstream
jiegec May 23, 2025
e8d28fa
rs: adapt to capstone v6 changes, mainly in aarch64
jiegec May 23, 2025
82776cf
rs: use aarch64_reg::Type for windows compat
jiegec May 23, 2025
b5ba6cd
rs: run cargo fmt to make ci happy
jiegec May 23, 2025
f819683
rs, sys: mention capstone 6.0.0-alpha4 and arch renaming in CHANGELOG
jiegec May 23, 2025
81b8f84
rs: avoid possible panics in library functions
jiegec May 23, 2025
c046d65
rs: add missing doc comments
jiegec May 23, 2025
cf181eb
rs, sys: generate arm_spsr_cspr_bits as bitfield enum
jiegec May 24, 2025
dbaa68d
rs: add previously failed testcase from issue 175
jiegec May 24, 2025
2434a33
ci: rename arch_arm64 to arch_aarch64 feature
jiegec May 24, 2025
fe0037b
sys: add Alpha arch support
jiegec May 24, 2025
30395c2
rs, sys: fix feature detection after renaming
jiegec May 24, 2025
4b82151
sys: add HPPA arch support
jiegec May 24, 2025
9262f5e
sys: add LoongArch arch support
jiegec May 24, 2025
0f406b2
sys: add Xtensa arch support
jiegec May 24, 2025
5de6e80
sys: add ARC arch support
jiegec May 24, 2025
4f00085
sys: move bpf bindings around to become in order
jiegec May 24, 2025
47ec2a7
rs: add Alpha arch support
jiegec May 24, 2025
2a17cf9
sys: fix build.rs lifetime for Rust 1.70.0
jiegec May 24, 2025
240bf5d
rs: add HPPA arch support
jiegec May 24, 2025
f16b5fd
rs: add LoongArch arch support
jiegec May 24, 2025
fd27c2c
rs: rename variable to reflect its type
jiegec May 24, 2025
82bf2e2
rs: disable failing hppa test due to upstream bug
jiegec May 24, 2025
bf6ed1f
rs: add Xtensa arch support
jiegec May 24, 2025
73c58d8
rs: fix tests on windows
jiegec May 24, 2025
65d5bdd
rs: add ARC arch support
jiegec May 24, 2025
f541a20
rs: fix type conversion on windows
jiegec May 24, 2025
265669b
rs: bump capstone to 6.0.0-Alpha4-8-gefc0ba44 to fix upstream bugs
jiegec May 26, 2025
b042b2a
rs: update tests after upstream bugs are fixed
jiegec May 26, 2025
804f160
rs: test CS_OPT_UNSIGNED using x86 code
jiegec May 26, 2025
9905c32
rs, sys: bump capstone to 6.0.0-Alpha4-13-gfe6bdc6e
jiegec Jun 15, 2025
202cf86
sys: bump capstone to 6.0.0-Alpha4-25-g717d8b05
jiegec Jul 9, 2025
f8f2520
rs: bump capstone to 6.0.0-Alpha4-25-g717d8b05
jiegec Jul 9, 2025
4b199bb
rs: add access mode to sparc operand
jiegec Jul 9, 2025
d878ee3
rs: document recent changes in CHANGELOG
jiegec Jul 9, 2025
05aea5d
rs: update tests for sparc, not a bug actually
jiegec Jul 9, 2025
6c99b35
rs: apply cargo clippy
jiegec Jul 9, 2025
0f57559
rs: fix tests on windows
jiegec Jul 9, 2025
36a2b30
rs, sys: bump capstone to 6.0.0-Alpha5
jiegec Aug 4, 2025
071ee66
rs: zero initialize cs_insn to make valgrind happy
jiegec Aug 4, 2025
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rs: add missing doc comments
  • Loading branch information
jiegec committed Aug 4, 2025
commit c046d65a60e7c1c3f822fa25fbefc5f00b5bc757
47 changes: 22 additions & 25 deletions capstone-rs/src/arch/aarch64.rs
Original file line number Diff line number Diff line change
Expand Up @@ -202,73 +202,70 @@ pub enum AArch64OperandType {
/// SMSTART/SMSTOP mode (Streaming SVE & ZA storage)
Svcr(AArch64Svcr),

///
/// Address translate operand
At(AArch64At),

///
/// Data barrier operand
Db(AArch64Db),

///
/// Data cache operand
Dc(AArch64Dc),

///
/// Instruction synchronization barrier operand
Isb(AArch64Isb),

///
/// Trace synchronization barrier operand
Tsb(AArch64Tsb),

///
/// Prefetch operand
Prfm(AArch64Prfm),

///
/// SVE prefetch operand
SvePrfm(AArch64SvePrfm),

///
/// Range prefetch operand
RPrfm(AArch64RPrfm),

///
/// PState field operand
PStateImm015(AArch64PStateImm015),

///
/// PState field operand
PStateImm01(AArch64PStateImm01),

///
/// Profiling synchronization barrier operand
Psb(AArch64Psb),

///
/// Branch target identification operand
Bti(AArch64Bti),

///
/// SVE predication pattern operand
SvePredPat(AArch64SvePredPat),

///
/// SVE vector length specifier
SveVecLenSpecifier(AArch64SveVecLenSpecifier),

///
/// SME operand
Sme(AArch64OpSme),

///
/// Immediate range
ImmRange(AArch64ImmRange),

///
/// TLB invalidate operand
Tlbi(AArch64Tlbi),

///
/// Instruction cache operand
Ic(AArch64Ic),

///
/// Synchronization instructions operand
Dbnxs(AArch64Dbnxs),

///
/// Exact floating point immediate operand
ExactFpImm(AArch64ExactFpImm),

///
/// System register
Sysreg(AArch64Sysreg),

///
SysImm(i32),

///
/// Predicate operand
Pred(AArch64OpPred),

/// Invalid
Expand Down