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adkian-sifive committed Nov 25, 2025
commit 22f570b3c0299d5f906e3a25d3f34cb56d022ca7
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Expand Up @@ -3,7 +3,7 @@
package chisel3.stage

import firrtl.options.Viewer.view
import firrtl.RenameMap
import firrtl.{RenameMap, seqToAnnoSeq}

import chisel3.ElaboratedCircuit
import chisel3.stage._
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Expand Up @@ -20,7 +20,7 @@ class AdderTreeTester(bitWidth: Int, numsToAdd: List[Int]) extends Module {
val dut = Module(new AdderTree(genType, numsToAdd.size))
dut.io.numIn := VecInit(numsToAdd.map(x => x.asUInt(bitWidth.W)))
val sumCorrect = dut.io.numOut === (numsToAdd.reduce(_ + _) % (1 << bitWidth)).asUInt(bitWidth.W)
assert(sumCorrect)
chisel3.assert(sumCorrect)
stop()
}

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Expand Up @@ -344,7 +344,7 @@ class AutoClonetypeSpec extends AnyFlatSpec with Matchers {
}
emitCHIRRTL {
new Module {
implicit val x = 8
implicit val x: Int = 8
val in = IO(Input(new MyBundle))
val out = IO(Output(new MyBundle))
out := in
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I'm surprised this file has so many lines added. Can you clarify what is going on?

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File renamed without changes.