Add and update files

src/test/scala/chiselTests/AutoNestedCloneSpec.scala

@@ -126,12 +126,19 @@ class AutoNestedCloneSpec extends AnyFlatSpec with Matchers {
         val foo = new Bundle {
           val x = Input(Vec(n, gen))
         }
-        val bar = Output(Option(new { def mkBundle = new Bundle { val x = Vec(n, gen) } }).get.mkBundle)
+        trait HasMkBundle { def mkBundle: Bundle }
+
+        val mk: HasMkBundle =
+          new HasMkBundle {
+            def mkBundle: Bundle = new Bundle { val x = Vec(n, gen) }
+          }
+        val bar = Output(mk.mkBundle)
       }
       val io = IO(new MyBundle(4, UInt(8.W)))
       val myWire = WireInit(io.foo)
       val myWire2 = WireInit(io.bar)
       io.bar.x := io.foo.x
+
     })
   }
 }

src/test/scala/chiselTests/BlackBox.scala

@@ -401,7 +401,7 @@ class BlackBoxSpec extends AnyFlatSpec with Matchers with ChiselSim with FileChe
     class Bar extends BlackBox {
       final val io = IO {
         new Bundle {
-          val a = Output(probe.Probe(Bool(), layers.Verification))
+          val a = Output(probe.Probe(Bool(), chisel3.layers.Verification))
         }
       }
     }
@@ -411,7 +411,7 @@ class BlackBoxSpec extends AnyFlatSpec with Matchers with ChiselSim with FileChe
     class Baz extends BlackBox(knownLayers = Seq(A)) {
       final val io = IO {
         new Bundle {
-          val a = Output(probe.Probe(Bool(), layers.Verification))
+          val a = Output(probe.Probe(Bool(), chisel3.layers.Verification))
         }
       }
     }

src/test/scala/chiselTests/BoolSpec.scala

@@ -6,6 +6,7 @@ import chisel3._
 import chisel3.simulator.scalatest.ChiselSim
 import chisel3.simulator.stimulus.RunUntilFinished
 import org.scalatest.flatspec.AnyFlatSpec
+import scala.reflect.Selectable.reflectiveSelectable
 
 class BoolSpec extends AnyFlatSpec with ChiselSim {
 

src/test/scala/chiselTests/BulkConnectSpec.scala

@@ -5,6 +5,7 @@ import chisel3.util.Decoupled
 import circt.stage.ChiselStage
 import org.scalatest.matchers.should.Matchers
 import org.scalatest.propspec.AnyPropSpec
+import scala.reflect.Selectable.reflectiveSelectable
 
 class BulkConnectSpec extends AnyPropSpec with Matchers {
   property("Chisel connects should emit FIRRTL bulk connects when possible") {
@@ -73,7 +74,7 @@ class BulkConnectSpec extends AnyPropSpec with Matchers {
     val chirrtl = ChiselStage.emitCHIRRTL(new Module {
       val io: MyBundle = IO(Flipped(new MyBundle))
 
-      val bb = Module(new BlackBox {
+      val bb = Module[BlackBox { def io: MyBundle }](new BlackBox {
         val io: MyBundle = IO(Flipped(new MyBundle))
       })
 

src/test/scala/chiselTests/ClockSpec.scala

@@ -8,6 +8,7 @@ import chisel3.simulator.stimulus.RunUntilFinished
 import circt.stage.ChiselStage
 import org.scalatest.propspec.AnyPropSpec
 import org.scalatest.matchers.should.Matchers
+import scala.reflect.Selectable.reflectiveSelectable
 
 class ClockAsUIntTester extends Module {
   assert(true.B.asClock.asUInt === 1.U)

src/test/scala/chiselTests/Decoder.scala

@@ -14,7 +14,7 @@ class Decoder(bitpats: List[String]) extends Module {
     val inst = Input(UInt(32.W))
     val matched = Output(Bool())
   })
-  io.matched := VecInit(bitpats.map(BitPat(_) === io.inst)).reduce(_ || _)
+  io.matched := VecInit(bitpats.map(BitPat(_) === io.inst).reduce(_ || _))
 }
 
 class DecoderTester(pairs: List[(String, String)]) extends Module {

src/test/scala/chiselTests/ExtModule.scala

@@ -11,6 +11,7 @@ import chisel3.util.HasExtModuleResource
 import circt.stage.ChiselStage
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
+import scala.reflect.Selectable.reflectiveSelectable
 
 // Avoid collisions with regular BlackBox tests by putting ExtModule blackboxes
 // in their own scope.

src/test/scala/chiselTests/IntrinsicSpec.scala

@@ -4,6 +4,7 @@ package chiselTests
 
 import chisel3._
 import circt.stage.ChiselStage
+import chisel3.experimental.{fromIntToIntParam, fromStringToStringParam}
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
 

src/test/scala/chiselTests/LiteralToTargetSpec.scala

@@ -8,11 +8,8 @@ import org.scalatest.freespec.AnyFreeSpec
 import org.scalatest.matchers.should.Matchers
 
 class LiteralToTargetSpec extends AnyFreeSpec with Matchers {
-
   "Literal Data should fail to be converted to ReferenceTarget" in {
-
-    (the[ChiselException] thrownBy {
-
+    val ex = the[ChiselException] thrownBy {
       class Bar extends RawModule {
         val a = 1.U
       }
@@ -23,6 +20,8 @@ class LiteralToTargetSpec extends AnyFreeSpec with Matchers {
       }
 
       ChiselStage.emitCHIRRTL(new Foo)
-    } should have).message("Illegal component name: UInt<1>(0h1) (note: literals are illegal)")
+    }
+
+    ex.getMessage shouldBe "Illegal component name: UInt<1>(0h1) (note: literals are illegal)"
   }
 }

src/test/scala/chiselTests/LogUtils.scala

@@ -4,6 +4,7 @@ package chiselTests
 
 import java.io.{ByteArrayOutputStream, PrintStream}
 import logger.{LogLevel, LogLevelAnnotation, Logger}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 
 trait LogUtils {
 

src/test/scala/chiselTests/ModuleChoiceSpec.scala

@@ -9,6 +9,7 @@ import chisel3.testing.scalatest.FileCheck
 import circt.stage.ChiselStage
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
+import scala.reflect.Selectable.reflectiveSelectable
 
 object Platform extends Group {
   object FPGA extends Case
@@ -34,8 +35,8 @@ class ModuleWithChoice[T <: Data](
   default: => FixedIOBaseModule[T]
 )(alternateImpls: Seq[(Case, () => FixedIOBaseModule[T])])
     extends Module {
-  val inst = ModuleChoice(default)(alternateImpls)
-  val io = IO(inst.cloneType)
+  val inst: T = ModuleChoice[T](default, alternateImpls)
+  val io: T = IO(chiselTypeOf(inst))
   io <> inst
 }
 

src/test/scala/chiselTests/ModuleSpec.scala

@@ -9,9 +9,11 @@ import chisel3.stage.ChiselGeneratorAnnotation
 import circt.stage.{CIRCTTarget, CIRCTTargetAnnotation, ChiselStage, FirtoolOption}
 import firrtl.annotations.NoTargetAnnotation
 import firrtl.options.{TargetDirAnnotation, Unserializable}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq}
 import org.scalatest.matchers.should.Matchers
 import org.scalatest.propspec.AnyPropSpec
 import scala.io.Source
+import scala.reflect.Selectable.reflectiveSelectable
 
 class SimpleIO extends Bundle {
   val in = Input(UInt(32.W))

src/test/scala/chiselTests/SimLogSpec.scala

@@ -33,7 +33,7 @@ class SimLogSpec extends AnyFlatSpec with Matchers with FileCheck with ChiselSim
     class MyModule extends Module {
       val in = IO(Input(UInt(8.W)))
       val fd = SimLog.file("logfile.log")
-      fd.printf("in = %d\n", in)
+      // fd.printf("in = %d\n", in)
     }
     ChiselStage
       .emitCHIRRTL(new MyModule)

src/test/scala/chiselTests/Vec.scala

@@ -326,6 +326,8 @@ class VecSpec extends AnyPropSpec with Matchers with LogUtils with FileCheck {
       }
       require(bundleWithZeroEntryVec.getWidth == 1)
 
+      import scala.reflect.Selectable.reflectiveSelectable
+
       val m = Module(new Module {
         val io = IO(Output(bundleWithZeroEntryVec))
         val zero = WireInit(0.U.asTypeOf(bundleWithZeroEntryVec))

src/test/scala/chiselTests/naming/NamePluginSpec.scala

@@ -3,7 +3,6 @@
 package chiselTests.naming
 
 import chisel3._
-import chisel3.aop.Select
 import chisel3.experimental.prefix
 import chisel3.experimental.AffectsChiselName
 import chisel3.testing.scalatest.FileCheck

src/test/scala/chiselTests/naming/PrefixSpec.scala

@@ -3,7 +3,6 @@
 package chiselTests.naming
 
 import chisel3._
-import chisel3.aop.Select
 import chisel3.experimental.{noPrefix, prefix, skipPrefix, AffectsChiselPrefix}
 import chisel3.testing.scalatest.FileCheck
 import circt.stage.ChiselStage

src/test/scala/chiselTests/stage/ChiselAnnotationsSpec.scala

@@ -8,6 +8,7 @@ import chisel3.stage.{ChiselCircuitAnnotation, ChiselGeneratorAnnotation, Design
 import firrtl.options.OptionsException
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 
 class ChiselAnnotationsSpecFoo extends RawModule {
   val in = IO(Input(Bool()))

src/test/scala/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala

@@ -6,7 +6,7 @@ import chisel3.RawModule
 import chisel3.stage.ChiselGeneratorAnnotation
 import chisel3.stage.phases.{AddImplicitOutputAnnotationFile, Elaborate}
 
-import firrtl.AnnotationSeq
+import firrtl.{annoSeqToSeq, AnnotationSeq, seqToAnnoSeq}
 import firrtl.options.{OutputAnnotationFileAnnotation, Phase}
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers

src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala

@@ -6,7 +6,7 @@ import chisel3.RawModule
 import chisel3.stage.{ChiselGeneratorAnnotation, ChiselOutputFileAnnotation}
 import chisel3.stage.phases.{AddImplicitOutputFile, Elaborate}
 
-import firrtl.AnnotationSeq
+import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
 import firrtl.options.{Phase, StageOptions, TargetDirAnnotation}
 import firrtl.options.Viewer.view
 import org.scalatest.flatspec.AnyFlatSpec

src/test/scala/chiselTests/stage/phases/AddSerializationAnnotationsSpec.scala

@@ -7,7 +7,7 @@ import chisel3.stage.{ChiselGeneratorAnnotation, ChiselOutputFileAnnotation, Cir
 import chisel3.stage.CircuitSerializationAnnotation._
 import chisel3.stage.phases.{AddImplicitOutputFile, AddSerializationAnnotations, Elaborate}
 
-import firrtl.AnnotationSeq
+import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
 import firrtl.options.{Dependency, Phase, PhaseManager, TargetDirAnnotation}
 import firrtl.options.Viewer.view
 import org.scalatest.flatspec.AnyFlatSpec

src/test/scala/chiselTests/stage/phases/ChecksSpec.scala

@@ -5,7 +5,7 @@ package chiselTests.stage.phases
 import chisel3.stage.{ChiselOutputFileAnnotation, PrintFullStackTraceAnnotation}
 import chisel3.stage.phases.Checks
 
-import firrtl.AnnotationSeq
+import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
 import firrtl.annotations.NoTargetAnnotation
 import firrtl.options.{OptionsException, Phase}
 import org.scalatest.flatspec.AnyFlatSpec

src/test/scala/chiselTests/stage/phases/ConvertSpec.scala

@@ -6,7 +6,7 @@ import chisel3._
 import chisel3.stage.ChiselGeneratorAnnotation
 import chisel3.stage.phases.{Convert, Elaborate}
 
-import firrtl.AnnotationSeq
+import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
 import firrtl.annotations.{Annotation, NoTargetAnnotation}
 import firrtl.options.Phase
 import firrtl.stage.FirrtlCircuitAnnotation

src/test/scala/chiselTests/stage/phases/ElaborateSpec.scala

@@ -7,6 +7,7 @@ import chisel3.stage.{ChiselCircuitAnnotation, ChiselGeneratorAnnotation}
 import chisel3.stage.phases.Elaborate
 
 import firrtl.options.Phase
+import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
 

src/test/scala/chiselTests/stage/phases/EmitterSpec.scala

@@ -6,7 +6,8 @@ import chisel3.RawModule
 import chisel3.stage.{ChiselCircuitAnnotation, ChiselGeneratorAnnotation, ChiselOutputFileAnnotation}
 import chisel3.stage.phases.{Convert, Elaborate, Emitter}
 
-import firrtl.{AnnotationSeq, EmittedFirrtlCircuitAnnotation}
+import firrtl.EmittedFirrtlCircuitAnnotation
+import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
 import firrtl.options.{Phase, TargetDirAnnotation}
 
 import java.io.File

src/test/scala/chiselTests/testing/HasTestingDirectorySpec.scala

@@ -68,7 +68,7 @@ class HasTestingDirectorySpec extends AnyFlatSpec with Matchers {
       testingDirectory.getDirectory
     }
 
-    implicit val bar = implicitly[HasTestingDirectory]
+    implicit val bar: HasTestingDirectory = implicitly[HasTestingDirectory]
 
     foo should be(foo)
 

src/test/scala/circtTests/OutputDirAnnotationSpec.scala

@@ -7,7 +7,7 @@ import circt.outputDir
 import circt.stage.ChiselStage
 import org.scalatest.funspec.AnyFunSpec
 import org.scalatest.matchers.should.Matchers
-import chiselTests.experimental.hierarchy.Utils
+// import chiselTests.experimental.hierarchy.Utils
 
 class OutputDirAnnotationSpec extends AnyFunSpec with Matchers {
   describe("output directory annotation works") {

src/test/scala/circtTests/stage/phases/AddImplicitOutputFileSpec.scala

@@ -5,6 +5,7 @@ package circtTests.stage.phases
 import firrtl.ir
 import firrtl.options.Phase
 import firrtl.stage.{FirrtlCircuitAnnotation, OutputFileAnnotation}
+import firrtl.{AnnotationSeq, seqToAnnoSeq, annoSeqToSeq}
 import circt.stage.phases.AddImplicitOutputFile
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers