Remove reflectiveSelectable import

src/test/scala-2/chisel3/util/BitPatSpec.scala

@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chisel3.util
+
+import chisel3._
+import chisel3.util.BitPat
+import _root_.circt.stage.ChiselStage
+import org.scalatest.flatspec.AnyFlatSpec
+import org.scalatest.matchers.should.Matchers
+
+object EnumExample extends ChiselEnum {
+  val VAL1, VAL2, VAL3 = Value
+}
+
+class BitPatSpec extends AnyFlatSpec with Matchers {
+  behavior.of(classOf[BitPat].toString)
+
+  it should "convert a BitPat to readable form" in {
+    val testPattern = "0" * 32 + "1" * 32 + "?" * 32 + "?01" * 32
+    BitPat("b" + testPattern).toString should be(s"BitPat($testPattern)")
+  }
+
+  it should "convert a BitPat to raw form" in {
+    val testPattern = "0" * 32 + "1" * 32 + "?" * 32 + "?01" * 32
+    BitPat("b" + testPattern).rawString should be(testPattern)
+  }
+
+  it should "not fail if BitPat width is 0" in {
+    intercept[IllegalArgumentException] { BitPat("b") }
+  }
+
+  it should "concat BitPat via ##" in {
+    (BitPat.Y(4) ## BitPat.dontCare(3) ## BitPat.N(2)).toString should be(s"BitPat(1111???00)")
+  }
+
+  it should "throw when BitPat apply to a Hardware" in {
+    intercept[java.lang.IllegalArgumentException] {
+      ChiselStage.emitCHIRRTL(new chisel3.Module {
+        BitPat(chisel3.Reg(chisel3.Bool()))
+      })
+    }
+  }
+
+  it should "index and return new BitPat" in {
+    val b = BitPat("b1001???")
+    b(0) should be(BitPat.dontCare(1))
+    b(6) should be(BitPat.Y())
+    b(5) should be(BitPat.N())
+  }
+
+  it should "slice and return new BitPat" in {
+    val b = BitPat("b1001???")
+    b(2, 0) should be(BitPat("b???"))
+    b(4, 3) should be(BitPat("b01"))
+    b(6, 6) should be(BitPat("b1"))
+  }
+
+  it should "parse UInt literals correctly" in {
+    BitPat(0.U) should be(new BitPat(0, 1, 1))
+    // Note that this parses as 1-bit width, there are other APIs that don't support zero-width UInts correctly
+    BitPat(0.U(0.W)) should be(new BitPat(0, 1, 1))
+    BitPat(1.U) should be(new BitPat(1, 1, 1))
+    BitPat(2.U) should be(new BitPat(2, 3, 2))
+    BitPat(0xdeadbeefL.U) should be(new BitPat(BigInt("deadbeef", 16), BigInt("ffffffff", 16), 32))
+  }
+
+  it should "support .hasDontCares" in {
+    BitPat("b?").hasDontCares should be(true)
+    BitPat("b??").hasDontCares should be(true)
+    BitPat("b0?").hasDontCares should be(true)
+    BitPat("b?1").hasDontCares should be(true)
+    BitPat("b0").hasDontCares should be(false)
+    BitPat("b10").hasDontCares should be(false)
+    BitPat("b01").hasDontCares should be(false)
+    BitPat(0xdeadbeefL.U).hasDontCares should be(false)
+    // Zero-width not supported yet
+    intercept[IllegalArgumentException] { BitPat("b").hasDontCares should be(false) }
+  }
+
+  it should "support .allZeros" in {
+    BitPat("b?").allZeros should be(false)
+    BitPat("b??").allZeros should be(false)
+    BitPat("b0?").allZeros should be(false)
+    BitPat("b?1").allZeros should be(false)
+    BitPat("b0").allZeros should be(true)
+    BitPat("b10").allZeros should be(false)
+    BitPat("b01").allZeros should be(false)
+    BitPat(0.U(128.W)).allZeros should be(true)
+    BitPat.N(23).allZeros should be(true)
+    BitPat(0xdeadbeefL.U).allZeros should be(false)
+    // Zero-width not supported yet
+    intercept[IllegalArgumentException] { BitPat("b").allZeros should be(true) }
+  }
+
+  it should "support .allOnes" in {
+    BitPat("b?").allOnes should be(false)
+    BitPat("b??").allOnes should be(false)
+    BitPat("b0?").allOnes should be(false)
+    BitPat("b?1").allOnes should be(false)
+    BitPat("b0").allOnes should be(false)
+    BitPat("b10").allOnes should be(false)
+    BitPat("b01").allOnes should be(false)
+    BitPat("b1").allOnes should be(true)
+    BitPat("b" + ("1" * 128)).allOnes should be(true)
+    BitPat.Y(23).allOnes should be(true)
+    BitPat(0xdeadbeefL.U).allOnes should be(false)
+    // Zero-width not supported yet
+    intercept[IllegalArgumentException] { BitPat("b").allOnes should be(true) }
+  }
+
+  it should "support .allDontCares" in {
+    BitPat("b?").allDontCares should be(true)
+    BitPat("b??").allDontCares should be(true)
+    BitPat("b0?").allDontCares should be(false)
+    BitPat("b?1").allDontCares should be(false)
+    BitPat("b0").allDontCares should be(false)
+    BitPat("b10").allDontCares should be(false)
+    BitPat("b1").allDontCares should be(false)
+    BitPat("b" + ("1" * 128)).allDontCares should be(false)
+    BitPat.dontCare(23).allDontCares should be(true)
+    BitPat(0xdeadbeefL.U).allDontCares should be(false)
+    // Zero-width not supported yet
+    intercept[IllegalArgumentException] { BitPat("b").allDontCares should be(true) }
+  }
+
+  it should "convert to BitPat from ChiselEnum" in {
+    val b = BitPat(EnumExample.VAL1)
+    val c = BitPat(EnumExample.VAL3)
+    b should be(BitPat("b00"))
+    c should be(BitPat("b10"))
+  }
+}

src/test/scala-2/chiselTests/AutoNestedCloneSpec.scala

@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiselTests
+
+import chisel3._
+import circt.stage.ChiselStage.emitCHIRRTL
+import org.scalatest.flatspec.AnyFlatSpec
+import org.scalatest.matchers.should.Matchers
+
+class BundleWithAnonymousInner(val w: Int) extends Bundle {
+  val inner = new Bundle {
+    val foo = Input(UInt(w.W))
+  }
+}
+
+class AutoNestedCloneSpec extends AnyFlatSpec with Matchers {
+
+  behavior.of("autoCloneType of inner Bundle in Chisel3")
+
+  it should "clone a doubly-nested inner bundle successfully" in {
+    emitCHIRRTL {
+      class Outer(val w: Int) extends Module {
+        class Middle(val w: Int) {
+          class InnerIOType extends Bundle {
+            val in = Input(UInt(w.W))
+          }
+          def getIO: InnerIOType = new InnerIOType
+        }
+        val io = IO(new Bundle {})
+        val myWire = Wire((new Middle(w)).getIO)
+      }
+      new Outer(2)
+    }
+  }
+
+  it should "clone an anonymous inner bundle successfully" in {
+    emitCHIRRTL {
+      class TestTop(val w: Int) extends Module {
+        val io = IO(new Bundle {})
+        val myWire = Wire(new Bundle { val a = UInt(w.W) })
+      }
+      new TestTop(2)
+    }
+  }
+
+  it should "pick the correct $outer instance for an anonymous inner bundle" in {
+    emitCHIRRTL {
+      class Inner(val w: Int) extends Module {
+        val io = IO(new Bundle {
+          val in = Input(UInt(w.W))
+          val out = Output(UInt(w.W))
+        })
+      }
+      class Outer(val w: Int) extends Module {
+        val io = IO(new Bundle {
+          val in = Input(UInt(w.W))
+          val out = Output(UInt(w.W))
+        })
+        val i = Module(new Inner(w))
+        val iw = Wire(chiselTypeOf(i.io))
+        iw <> io
+        i.io <> iw
+      }
+      new Outer(2)
+    }
+  }
+
+  it should "clone an anonymous, bound, inner bundle of another bundle successfully" in {
+    emitCHIRRTL {
+      class TestModule(w: Int) extends Module {
+        val io = IO(new BundleWithAnonymousInner(w))
+        val w0 = WireDefault(io)
+        val w1 = WireDefault(io.inner)
+      }
+      new TestModule(8)
+    }
+  }
+
+  it should "clone an anonymous, inner bundle of a Module, bound to another bundle successfully" in {
+    emitCHIRRTL {
+      class TestModule(w: Int) extends Module {
+        val bun = new Bundle {
+          val foo = UInt(w.W)
+        }
+        val io = IO(new Bundle {
+          val inner = Input(bun)
+        })
+        val w0 = WireDefault(io)
+        val w1 = WireDefault(io.inner)
+      }
+      new TestModule(8)
+    }
+  }
+
+  it should "clone a double-nested anonymous Bundle" in {
+    emitCHIRRTL {
+      class TestModule() extends Module {
+        val io = IO(new Bundle {
+          val inner = Input(new Bundle {
+            val x = UInt(8.W)
+          })
+        })
+      }
+      new TestModule()
+    }
+  }
+
+  it should "support an anonymous doubly-nested inner bundle" in {
+    emitCHIRRTL {
+      class Outer(val w: Int) extends Module {
+        class Middle(val w: Int) {
+          def getIO: Bundle = new Bundle {
+            val in = Input(UInt(w.W))
+          }
+        }
+        val io = IO(new Bundle {})
+        val myWire = Wire((new Middle(w)).getIO)
+      }
+      new Outer(2)
+    }
+  }
+
+  it should "support anonymous Inner bundles that capture type parameters from outer Bundles" in {
+    emitCHIRRTL(new Module {
+      class MyBundle[T <: Data](n: Int, gen: T) extends Bundle {
+        val foo = new Bundle {
+          val x = Input(Vec(n, gen))
+        }
+        val bar = Output(Option(new { def mkBundle = new Bundle { val x = Vec(n, gen) } }).get.mkBundle)
+      }
+      val io = IO(new MyBundle(4, UInt(8.W)))
+      val myWire = WireInit(io.foo)
+      val myWire2 = WireInit(io.bar)
+      io.bar.x := io.foo.x
+    })
+  }
+}

src/test/scala-2/chiselTests/ProbeSpec.scala

@@ -12,7 +12,6 @@ import chisel3.testing.scalatest.FileCheck
 import circt.stage.ChiselStage
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
-import scala.reflect.Selectable.reflectiveSelectable
 
 class ProbeSpec extends AnyFlatSpec with Matchers with FileCheck with ChiselSim {
   // Strip SourceInfos and split into lines