add gicv3

Makefile

@@ -58,6 +58,7 @@ GRAPHIC ?= n
 V9P ?= n
 BUS ?= mmio
 RISCV_BIOS ?= default
+GICV3 ?= n
 
 DISK_IMG ?= disk.img
 QEMU_LOG ?= n

api/ruxfeat/Cargo.toml

@@ -22,6 +22,7 @@ fp_simd = ["ruxhal/fp_simd", "ruxfs/fp_simd"]
 
 # Interrupts
 irq = ["ruxhal/irq", "ruxruntime/irq", "ruxtask?/irq"]
+gic-v3 = ["ruxhal/gic-v3"]
 
 # Real time clock
 rtc = ["ruxhal/rtc", "ruxruntime/rtc"]

api/ruxos_posix_api/src/imp/mmap/trap.rs

@@ -40,6 +40,7 @@ struct TrapHandlerImpl;
 #[crate_interface::impl_interface]
 impl ruxhal::trap::TrapHandler for TrapHandlerImpl {
     fn handle_page_fault(vaddr: usize, cause: PageFaultCause) -> bool {
+        info!("lhw debug in handle_page_fault addr {:x} case {:?}",vaddr, cause);
         let binding_task = current();
         let mut binding_mem_map = binding_task.mm.vma_map.lock();
         let vma_map = binding_mem_map.deref_mut();

crates/arm_gic/Cargo.toml

@@ -9,5 +9,10 @@ homepage = "https://github.com/rcore-os/arceos"
 repository = "https://github.com/rcore-os/arceos/tree/main/crates/arm_gic"
 documentation = "https://rcore-os.github.io/arceos/arm_gic/index.html"
 
+[features]
+default = []
+gic-v3 = []
+
 [dependencies]
 tock-registers = "0.8"
+log = "0.4"

crates/arm_gic/src/gic_v2.rs

@@ -13,7 +13,7 @@
 
 use core::ptr::NonNull;
 
-use crate::{TriggerMode, GIC_MAX_IRQ, SPI_RANGE};
+use crate::{TriggerMode, GIC_MAX_IRQ, SPI_RANGE, read_sysreg, write_sysreg};
 use tock_registers::interfaces::{Readable, Writeable};
 use tock_registers::register_structs;
 use tock_registers::registers::{ReadOnly, ReadWrite, WriteOnly};
@@ -218,6 +218,8 @@ impl GicDistributor {
     }
 }
 
+use log::info;
+
 impl GicCpuInterface {
     /// Construct a new GIC CPU interface instance from the base address.
     pub const fn new(base: *mut u8) -> Self {
@@ -277,7 +279,7 @@ impl GicCpuInterface {
     /// This function should be called only once.
     pub fn init(&self) {
         // enable GIC0
-        self.regs().CTLR.set(1);
+        self.regs().CTLR.set(0x1);
         // unmask interrupts at all priority levels
         self.regs().PMR.set(0xff);
     }