Skip to content

[Arm64] Vector Load/Store structure instructions #33461

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
echesakov merged 24 commits into from
Mar 14, 2020
Merged

[Arm64] Vector Load/Store structure instructions #33461

Show file tree
Hide file tree
Changes from 1 commit
Commits
Show all changes
24 commits
Select commit Hold shift + click to select a range
e31f305
Update ld1 in instrsarm64.h
echesakov Mar 10, 2020
cddcb09
Add ld2, ld3, ld4, st1, st2, st3, st4 in instrsarm64.h
echesakov Mar 10, 2020
d11a956
Add ld1, st1 operating on multiple registers in instrsarm64.h
echesakov Mar 10, 2020
66cb52e
Add ld1r, ld2r, ld3r, ld4r in instrsarm64.h
echesakov Mar 10, 2020
d591c2b
Remove EN4J, add EN6B and EN3J in emitarm64.cpp emitfmtsarm64.h
echesakov Mar 10, 2020
b559403
Update LS_2D, LS_2E, LS_3F, LS_3G and add LS_2F, LS_2G in emitfmtsarm…
echesakov Mar 10, 2020
e8524fe
Add Arm64 emitter unit tests for "Load/Store Vector" instructions in …
echesakov Mar 3, 2020
b4aa743
Add emitter::emitDispElemsize in emitarm64.cpp emitarm64.h
echesakov Mar 10, 2020
4e1ce14
Update functions' headers in emitarm64.cpp
echesakov Mar 10, 2020
9cca19b
Add emitDispVectorRegList and emitDispVectorElemList in emitarm64.cpp…
echesakov Mar 10, 2020
cd88213
Add insGetLoadStoreVectorSelem in emitarm64.cpp emitarm64.h
echesakov Mar 10, 2020
8fe0715
Update emitIns_R_R in emitarm64.cpp
echesakov Mar 10, 2020
e7ce778
Update emitIns_R_R_I in emitarm64.cpp
echesakov Mar 11, 2020
b493842
Update emitIns_R_R_I in emitarm64.cpp
echesakov Mar 11, 2020
ee4415b
Update emitIns_R_R_R in emitarm64.cpp
echesakov Mar 10, 2020
bdc9df6
Update emitIns_R_R_R_I in emitarm64.cpp
echesakov Mar 10, 2020
66103d5
Update emitIns_R_R_I_I in emitarm64.cpp emitarm64.h
echesakov Mar 10, 2020
a0bfd42
Update emitDispIns in emitarm64.cpp
echesakov Mar 10, 2020
e77156b
Update emitOutputInstr in emitarm64.cpp
echesakov Mar 11, 2020
43aed1d
Update emitInsSanityCheck in emitarm64.cpp
echesakov Mar 11, 2020
683a20d
Update emitInsMayWriteToGCReg in emitarm64.cpp
echesakov Mar 11, 2020
6a53804
Remove ld1 in emitInsTargetRegSize in emitarm64.cpp
echesakov Mar 11, 2020
1e482c5
Update getMemoryOperation and getInsExecutionCharacteristics in emit.…
echesakov Mar 11, 2020
c7af7d2
Address Tanner's feedback on GitHub.
echesakov Mar 13, 2020
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
Prev Previous commit
Next Next commit
Update emitIns_R_R_I_I in emitarm64.cpp emitarm64.h 
* Load/Store single structure  post-indexed by an immediate
  • Loading branch information
@echesakov
echesakov committed Mar 11, 2020
commit 66103d5f015f96956e3d762c819ecd8fd25b86e2
34 changes: 33 additions & 1 deletion src/coreclr/src/jit/emitarm64.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6282,7 +6282,8 @@ void emitter::emitIns_R_R_R_Ext(instruction ins,
* Add an instruction referencing two registers and two constants.
*/

void emitter::emitIns_R_R_I_I(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, int imm1, int imm2)
void emitter::emitIns_R_R_I_I(
instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, int imm1, int imm2, insOpts opt)
{
emitAttr size = EA_SIZE(attr);
emitAttr elemsize = EA_UNKNOWN;
Expand All @@ -6295,6 +6296,7 @@ void emitter::emitIns_R_R_I_I(instruction ins, emitAttr attr, regNumber reg1, re
int lsb;
int width;
bitMaskImm bmi;
unsigned selem;

case INS_bfm:
case INS_sbfm:
Expand All @@ -6303,6 +6305,7 @@ void emitter::emitIns_R_R_I_I(instruction ins, emitAttr attr, regNumber reg1, re
assert(isGeneralRegister(reg2));
assert(isValidImmShift(imm1, size));
assert(isValidImmShift(imm2, size));
assert(insOptsNone(opt));
bmi.immNRS = 0;
bmi.immN = (size == EA_8BYTE);
bmi.immR = imm1;
Expand All @@ -6320,6 +6323,7 @@ void emitter::emitIns_R_R_I_I(instruction ins, emitAttr attr, regNumber reg1, re
width = imm2 - 1;
assert(isValidImmShift(lsb, size));
assert(isValidImmShift(width, size));
assert(insOptsNone(opt));
bmi.immNRS = 0;
bmi.immN = (size == EA_8BYTE);
bmi.immR = lsb;
Expand All @@ -6337,6 +6341,7 @@ void emitter::emitIns_R_R_I_I(instruction ins, emitAttr attr, regNumber reg1, re
width = imm2 + imm1 - 1;
assert(isValidImmShift(lsb, size));
assert(isValidImmShift(width, size));
assert(insOptsNone(opt));
bmi.immNRS = 0;
bmi.immN = (size == EA_8BYTE);
bmi.immR = imm1;
Expand All @@ -6353,10 +6358,36 @@ void emitter::emitIns_R_R_I_I(instruction ins, emitAttr attr, regNumber reg1, re
assert(isValidVectorElemsize(elemsize));
assert(isValidVectorIndex(EA_16BYTE, elemsize, imm1));
assert(isValidVectorIndex(EA_16BYTE, elemsize, imm2));
assert(insOptsNone(opt));
immOut = (imm1 << 4) + imm2;
fmt = IF_DV_2F;
break;

case INS_ld1:
case INS_ld2:
case INS_ld3:
case INS_ld4:
case INS_st1:
case INS_st2:
case INS_st3:
case INS_st4:
assert(isVectorRegister(reg1));
assert(isGeneralRegisterOrSP(reg2));

elemsize = size;
assert(isValidVectorElemsize(elemsize));
assert(isValidVectorIndex(EA_16BYTE, elemsize, imm1));

selem = insGetLoadStoreVectorSelem(ins);
assert((elemsize * selem) == (unsigned)imm2);
assert(insOptsPostIndex(opt));

// Load/Store single structure post-indexed by an immediate
reg2 = encodingSPtoZR(reg2);
immOut = imm1;
fmt = IF_LS_2G;
break;

default:
unreached();
break;
Expand All @@ -6367,6 +6398,7 @@ void emitter::emitIns_R_R_I_I(instruction ins, emitAttr attr, regNumber reg1, re

id->idIns(ins);
id->idInsFmt(fmt);
id->idInsOpt(opt);

id->idReg1(reg1);
id->idReg2(reg2);
Expand Down
3 changes: 2 additions & 1 deletion src/coreclr/src/jit/emitarm64.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -743,7 +743,8 @@ void emitIns_R_R_R_Ext(instruction ins,
insOpts opt = INS_OPTS_NONE,
int shiftAmount = -1);

void emitIns_R_R_I_I(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, int imm1, int imm2);
void emitIns_R_R_I_I(
instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, int imm1, int imm2, insOpts opt = INS_OPTS_NONE);

void emitIns_R_R_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3, regNumber reg4);

Expand Down