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[Arm64] Vector Load/Store structure instructions #33461

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Merged
echesakov merged 24 commits into from
Mar 14, 2020
Merged

[Arm64] Vector Load/Store structure instructions #33461

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e31f305
Update ld1 in instrsarm64.h
echesakov Mar 10, 2020
cddcb09
Add ld2, ld3, ld4, st1, st2, st3, st4 in instrsarm64.h
echesakov Mar 10, 2020
d11a956
Add ld1, st1 operating on multiple registers in instrsarm64.h
echesakov Mar 10, 2020
66cb52e
Add ld1r, ld2r, ld3r, ld4r in instrsarm64.h
echesakov Mar 10, 2020
d591c2b
Remove EN4J, add EN6B and EN3J in emitarm64.cpp emitfmtsarm64.h
echesakov Mar 10, 2020
b559403
Update LS_2D, LS_2E, LS_3F, LS_3G and add LS_2F, LS_2G in emitfmtsarm…
echesakov Mar 10, 2020
e8524fe
Add Arm64 emitter unit tests for "Load/Store Vector" instructions in …
echesakov Mar 3, 2020
b4aa743
Add emitter::emitDispElemsize in emitarm64.cpp emitarm64.h
echesakov Mar 10, 2020
4e1ce14
Update functions' headers in emitarm64.cpp
echesakov Mar 10, 2020
9cca19b
Add emitDispVectorRegList and emitDispVectorElemList in emitarm64.cpp…
echesakov Mar 10, 2020
cd88213
Add insGetLoadStoreVectorSelem in emitarm64.cpp emitarm64.h
echesakov Mar 10, 2020
8fe0715
Update emitIns_R_R in emitarm64.cpp
echesakov Mar 10, 2020
e7ce778
Update emitIns_R_R_I in emitarm64.cpp
echesakov Mar 11, 2020
b493842
Update emitIns_R_R_I in emitarm64.cpp
echesakov Mar 11, 2020
ee4415b
Update emitIns_R_R_R in emitarm64.cpp
echesakov Mar 10, 2020
bdc9df6
Update emitIns_R_R_R_I in emitarm64.cpp
echesakov Mar 10, 2020
66103d5
Update emitIns_R_R_I_I in emitarm64.cpp emitarm64.h
echesakov Mar 10, 2020
a0bfd42
Update emitDispIns in emitarm64.cpp
echesakov Mar 10, 2020
e77156b
Update emitOutputInstr in emitarm64.cpp
echesakov Mar 11, 2020
43aed1d
Update emitInsSanityCheck in emitarm64.cpp
echesakov Mar 11, 2020
683a20d
Update emitInsMayWriteToGCReg in emitarm64.cpp
echesakov Mar 11, 2020
6a53804
Remove ld1 in emitInsTargetRegSize in emitarm64.cpp
echesakov Mar 11, 2020
1e482c5
Update getMemoryOperation and getInsExecutionCharacteristics in emit.…
echesakov Mar 11, 2020
c7af7d2
Address Tanner's feedback on GitHub.
echesakov Mar 13, 2020
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Update emitDispIns in emitarm64.cpp
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@echesakov
echesakov committed Mar 11, 2020
commit a0bfd420538ca0c41c15c7e59e5f5bb78d3c6ec5
76 changes: 54 additions & 22 deletions src/coreclr/src/jit/emitarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -11429,6 +11429,7 @@ void emitter::emitDispIns(
emitAttr dstsize;
ssize_t index;
ssize_t index2;
unsigned selem;

case IF_BI_0A: // BI_0A ......iiiiiiiiii iiiiiiiiiiiiiiii simm26:00
case IF_BI_0B: // BI_0B ......iiiiiiiiii iiiiiiiiiii..... simm19:00
Expand Down Expand Up @@ -11603,17 +11604,41 @@ void emitter::emitDispIns(
emitDispAddrRI(id->idReg2(), id->idInsOpt(), imm);
break;

case IF_LS_2D: // LS_2D .Q.............. xx.xssnnnnnttttt Vt Rn
assert(emitGetInsSC(id) == 0);
emitDispReg(id->idReg1(), emitInsTargetRegSize(id), true);
emitDispAddrRI(id->idReg2(), id->idInsOpt(), 0);
case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
selem = insGetLoadStoreVectorSelem(id->idIns());
emitDispVectorRegList(id->idReg1(), selem, id->idInsOpt(), true);

if (fmt == IF_LS_2D)
{
// Load/Store multiple structures base register
// Load single structure and replicate base register
emitDispAddrRI(id->idReg2(), INS_OPTS_NONE, 0);
}
else
{
// Load/Store multiple structures post-indexed by an immediate
// Load single structure and replicate post-indexed by an immediate
emitDispAddrRI(id->idReg2(), INS_OPTS_POST_INDEX, id->idSmallCns());
}
break;

case IF_LS_2E: // LS_2E .Q.............. xx.Sssnnnnnttttt Vt[] Rn
assert(insOptsNone(id->idInsOpt()));
assert(emitGetInsSC(id) == 0);
emitDispReg(id->idReg1(), emitInsTargetRegSize(id), true);
emitDispAddrRI(id->idReg2(), id->idInsOpt(), 0);
case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
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@briansull briansull Mar 13, 2020 •
edited
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This should have the xx fields as well:

.Q.............. xx.Sssnnnnnttttt Vt[] Rn

selem = insGetLoadStoreVectorSelem(id->idIns());
elemsize = id->idOpSize();
emitDispVectorElemList(id->idReg1(), selem, elemsize, id->idSmallCns(), true);

if (fmt == IF_LS_2F)
{
// Load/Store single structure base register
emitDispAddrRI(id->idReg2(), INS_OPTS_NONE, 0);
}
else
{
// Load/Store single structure post-indexed by an immediate
emitDispAddrRI(id->idReg2(), INS_OPTS_POST_INDEX, (selem * elemsize));
}
break;

case IF_LS_3A: // LS_3A .X.......X.mmmmm oooS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
Expand Down Expand Up @@ -11662,20 +11687,27 @@ void emitter::emitDispIns(
emitDispAddrRI(id->idReg3(), id->idInsOpt(), 0);
break;

case IF_LS_3F: // LS_3F .Q.........mmmmm xx.xssnnnnnttttt Vt Rn Rm
assert(insOptsNone(id->idInsOpt()));
assert(emitGetInsSC(id) == 0);
emitDispReg(id->idReg1(), emitInsTargetRegSize(id), true);
emitDispReg(id->idReg2(), emitInsTargetRegSize(id), true);
emitDispAddrRI(id->idReg3(), id->idInsOpt(), 0);
break;
case IF_LS_3F: // LS_3F .Q.........mmmmm ....ssnnnnnttttt Vt Rn Rm
case IF_LS_3G: // LS_3G .Q.........mmmmm ...Sssnnnnnttttt Vt[] Rn Rm
selem = insGetLoadStoreVectorSelem(id->idIns());

case IF_LS_3G: // LS_3G .Q.........mmmmm xx.Sssnnnnnttttt Vt[] Rn Rm
assert(insOptsNone(id->idInsOpt()));
assert(emitGetInsSC(id) == 0);
emitDispReg(id->idReg1(), emitInsTargetRegSize(id), true);
emitDispReg(id->idReg2(), emitInsTargetRegSize(id), true);
emitDispAddrRI(id->idReg3(), id->idInsOpt(), 0);
if (fmt == IF_LS_3F)
{
// Load/Store multiple structures post-indexed by a register
// Load single structure and replicate post-indexed by a register
emitDispVectorRegList(id->idReg1(), selem, id->idInsOpt(), true);
}
else
{
// Load/Store single structure post-indexed by a register
elemsize = id->idOpSize();
emitDispVectorElemList(id->idReg1(), selem, elemsize, id->idSmallCns(), true);
}

printf("[");
emitDispReg(encodingZRtoSP(id->idReg2()), EA_8BYTE, false);
printf("], ");
emitDispReg(id->idReg3(), EA_8BYTE, false);
break;

case IF_DI_1A: // DI_1A X.......shiiiiii iiiiiinnnnn..... Rn imm(i12,sh)
Expand Down