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[Arm64] Vector Load/Store structure instructions #33461

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Merged
echesakov merged 24 commits into from
Mar 14, 2020
Merged

[Arm64] Vector Load/Store structure instructions #33461

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e31f305
Update ld1 in instrsarm64.h
echesakov Mar 10, 2020
cddcb09
Add ld2, ld3, ld4, st1, st2, st3, st4 in instrsarm64.h
echesakov Mar 10, 2020
d11a956
Add ld1, st1 operating on multiple registers in instrsarm64.h
echesakov Mar 10, 2020
66cb52e
Add ld1r, ld2r, ld3r, ld4r in instrsarm64.h
echesakov Mar 10, 2020
d591c2b
Remove EN4J, add EN6B and EN3J in emitarm64.cpp emitfmtsarm64.h
echesakov Mar 10, 2020
b559403
Update LS_2D, LS_2E, LS_3F, LS_3G and add LS_2F, LS_2G in emitfmtsarm…
echesakov Mar 10, 2020
e8524fe
Add Arm64 emitter unit tests for "Load/Store Vector" instructions in …
echesakov Mar 3, 2020
b4aa743
Add emitter::emitDispElemsize in emitarm64.cpp emitarm64.h
echesakov Mar 10, 2020
4e1ce14
Update functions' headers in emitarm64.cpp
echesakov Mar 10, 2020
9cca19b
Add emitDispVectorRegList and emitDispVectorElemList in emitarm64.cpp…
echesakov Mar 10, 2020
cd88213
Add insGetLoadStoreVectorSelem in emitarm64.cpp emitarm64.h
echesakov Mar 10, 2020
8fe0715
Update emitIns_R_R in emitarm64.cpp
echesakov Mar 10, 2020
e7ce778
Update emitIns_R_R_I in emitarm64.cpp
echesakov Mar 11, 2020
b493842
Update emitIns_R_R_I in emitarm64.cpp
echesakov Mar 11, 2020
ee4415b
Update emitIns_R_R_R in emitarm64.cpp
echesakov Mar 10, 2020
bdc9df6
Update emitIns_R_R_R_I in emitarm64.cpp
echesakov Mar 10, 2020
66103d5
Update emitIns_R_R_I_I in emitarm64.cpp emitarm64.h
echesakov Mar 10, 2020
a0bfd42
Update emitDispIns in emitarm64.cpp
echesakov Mar 10, 2020
e77156b
Update emitOutputInstr in emitarm64.cpp
echesakov Mar 11, 2020
43aed1d
Update emitInsSanityCheck in emitarm64.cpp
echesakov Mar 11, 2020
683a20d
Update emitInsMayWriteToGCReg in emitarm64.cpp
echesakov Mar 11, 2020
6a53804
Remove ld1 in emitInsTargetRegSize in emitarm64.cpp
echesakov Mar 11, 2020
1e482c5
Update getMemoryOperation and getInsExecutionCharacteristics in emit.…
echesakov Mar 11, 2020
c7af7d2
Address Tanner's feedback on GitHub.
echesakov Mar 13, 2020
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Update LS_2D, LS_2E, LS_3F, LS_3G and add LS_2F, LS_2G in emitfmtsarm… 
…64.h
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@echesakov
echesakov committed Mar 11, 2020
commit b5594035a740825f0e0fb5dbafe99faa1b45239d
13 changes: 9 additions & 4 deletions src/coreclr/src/jit/emitfmtsarm64.h
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Expand Up @@ -134,15 +134,20 @@ IF_DEF(LS_1A, IS_NONE, JMP) // LS_1A XX...V..iiiiiiii iiiiiiiiiiittttt R
IF_DEF(LS_2A, IS_NONE, NONE) // LS_2A .X.......X...... ......nnnnnttttt Rt Rn
IF_DEF(LS_2B, IS_NONE, NONE) // LS_2B .X.......Xiiiiii iiiiiinnnnnttttt Rt Rn imm(0-4095)
IF_DEF(LS_2C, IS_NONE, NONE) // LS_2C .X.......X.iiiii iiiiP.nnnnnttttt Rt Rn imm(-256..+255) pre/post inc
IF_DEF(LS_2D, IS_NONE, NONE) // LS_2D .Q.............. xx.xssnnnnnttttt Rn Vt
IF_DEF(LS_2E, IS_NONE, NONE) // LS_2E .Q.............. xx.Sssnnnnnttttt Rn Vt[]
IF_DEF(LS_2D, IS_NONE, NONE) // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn Load/Store multiple structures base register
// Load single structure and replicate base register
IF_DEF(LS_2E, IS_NONE, NONE) // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn Load/Store multiple structures post-indexed by an immediate
// Load single structure and replicate post-indexed by an immediate
IF_DEF(LS_2F, IS_NONE, NONE) // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure base register
IF_DEF(LS_2G, IS_NONE, NONE) // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn Load/Store single structure post-indexed by an immediate
IF_DEF(LS_3A, IS_NONE, NONE) // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
IF_DEF(LS_3B, IS_NONE, NONE) // LS_3B X............... .aaaaannnnnddddd Rd Ra Rn
IF_DEF(LS_3C, IS_NONE, NONE) // LS_3C X.........iiiiii iaaaaannnnnddddd Rd Ra Rn imm(im7,sh)
IF_DEF(LS_3D, IS_NONE, NONE) // LS_3D .X.......X.mmmmm ......nnnnnttttt Wm Rt Rn
IF_DEF(LS_3E, IS_NONE, NONE) // LS_3E .X.........mmmmm ......nnnnnttttt Rm Rt Rn ARMv8.1 LSE Atomics
IF_DEF(LS_3F, IS_NONE, NONE) // LS_3F .Q.........mmmmm xx.xssnnnnnttttt Rm Rn Vt
IF_DEF(LS_3G, IS_NONE, NONE) // LS_3G .Q.........mmmmm xx.Sssnnnnnttttt Rm Rn Vt[]
IF_DEF(LS_3F, IS_NONE, NONE) // LS_3F .Q.........mmmmm ....ssnnnnnttttt Vt Rn Rm Load/Store multiple structures post-indexed by a register
// Load single structure and replicate post-indexed by a register
IF_DEF(LS_3G, IS_NONE, NONE) // LS_3G .Q.........mmmmm ...Sssnnnnnttttt Vt[] Rn Rm Load/Store single structure post-indexed by a register

IF_DEF(DI_1A, IS_NONE, NONE) // DI_1A X.......shiiiiii iiiiiinnnnn..... Rn imm(i12,sh)
IF_DEF(DI_1B, IS_NONE, NONE) // DI_1B X........hwiiiii iiiiiiiiiiiddddd Rd imm(i16,hw)
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