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[Arm64] Vector Load/Store structure instructions #33461

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Merged
echesakov merged 24 commits into from
Mar 14, 2020
Merged

[Arm64] Vector Load/Store structure instructions #33461

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e31f305
Update ld1 in instrsarm64.h
echesakov Mar 10, 2020
cddcb09
Add ld2, ld3, ld4, st1, st2, st3, st4 in instrsarm64.h
echesakov Mar 10, 2020
d11a956
Add ld1, st1 operating on multiple registers in instrsarm64.h
echesakov Mar 10, 2020
66cb52e
Add ld1r, ld2r, ld3r, ld4r in instrsarm64.h
echesakov Mar 10, 2020
d591c2b
Remove EN4J, add EN6B and EN3J in emitarm64.cpp emitfmtsarm64.h
echesakov Mar 10, 2020
b559403
Update LS_2D, LS_2E, LS_3F, LS_3G and add LS_2F, LS_2G in emitfmtsarm…
echesakov Mar 10, 2020
e8524fe
Add Arm64 emitter unit tests for "Load/Store Vector" instructions in …
echesakov Mar 3, 2020
b4aa743
Add emitter::emitDispElemsize in emitarm64.cpp emitarm64.h
echesakov Mar 10, 2020
4e1ce14
Update functions' headers in emitarm64.cpp
echesakov Mar 10, 2020
9cca19b
Add emitDispVectorRegList and emitDispVectorElemList in emitarm64.cpp…
echesakov Mar 10, 2020
cd88213
Add insGetLoadStoreVectorSelem in emitarm64.cpp emitarm64.h
echesakov Mar 10, 2020
8fe0715
Update emitIns_R_R in emitarm64.cpp
echesakov Mar 10, 2020
e7ce778
Update emitIns_R_R_I in emitarm64.cpp
echesakov Mar 11, 2020
b493842
Update emitIns_R_R_I in emitarm64.cpp
echesakov Mar 11, 2020
ee4415b
Update emitIns_R_R_R in emitarm64.cpp
echesakov Mar 10, 2020
bdc9df6
Update emitIns_R_R_R_I in emitarm64.cpp
echesakov Mar 10, 2020
66103d5
Update emitIns_R_R_I_I in emitarm64.cpp emitarm64.h
echesakov Mar 10, 2020
a0bfd42
Update emitDispIns in emitarm64.cpp
echesakov Mar 10, 2020
e77156b
Update emitOutputInstr in emitarm64.cpp
echesakov Mar 11, 2020
43aed1d
Update emitInsSanityCheck in emitarm64.cpp
echesakov Mar 11, 2020
683a20d
Update emitInsMayWriteToGCReg in emitarm64.cpp
echesakov Mar 11, 2020
6a53804
Remove ld1 in emitInsTargetRegSize in emitarm64.cpp
echesakov Mar 11, 2020
1e482c5
Update getMemoryOperation and getInsExecutionCharacteristics in emit.…
echesakov Mar 11, 2020
c7af7d2
Address Tanner's feedback on GitHub.
echesakov Mar 13, 2020
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Address Tanner's feedback on GitHub.
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@echesakov
echesakov committed Mar 13, 2020
commit c7af7d2e3b26529c3b0812d286fc8215b5654279
78 changes: 49 additions & 29 deletions src/coreclr/src/jit/emitarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1264,7 +1264,15 @@ static const char * const bRegNames[] =
// clang-format on

//------------------------------------------------------------------------
// emitRegName: Returns a string that a general-purpose register name or SIMD and floating-point scalar register name
// emitRegName: Returns a general-purpose register name or SIMD and floating-point scalar register name.
//
// Arguments:
// reg - A general-purpose register or SIMD and floating-point register.
// size - A register size.
// varName - unused parameter.
//
// Return value:
// A string that represents a general-purpose register name or SIMD and floating-point scalar register name.
//
const char* emitter::emitRegName(regNumber reg, emitAttr size, bool varName)
{
Expand Down Expand Up @@ -1302,7 +1310,13 @@ const char* emitter::emitRegName(regNumber reg, emitAttr size, bool varName)
}

//------------------------------------------------------------------------
// emitVectorRegName: Returns a string that represents a SIMD vector register name
// emitVectorRegName: Returns a SIMD vector register name.
//
// Arguments:
// reg - A SIMD and floating-point register.
//
// Return value:
// A string that represents a SIMD vector register name.
//
const char* emitter::emitVectorRegName(regNumber reg)
{
Expand Down Expand Up @@ -3230,50 +3244,56 @@ emitter::code_t emitter::emitInsCode(instruction ins, insFormat fmt)
}

//------------------------------------------------------------------------
// insGetLoadStoreVectorSelem: Returns a number of structure elements for a Load/Store Vector instruction
// insGetLoadStoreRegisterListSize: Returns a size of the register list a given instruction operates on.
//
/*static*/ unsigned emitter::insGetLoadStoreVectorSelem(instruction ins)
// Arguments:
// ins - A Load/Store Vector instruction (e.g. ld1 (2 registers), ld1r, st1).
//
// Return value:
// A number of consecutive SIMD and floating-point registers the instruction loads to/store from.
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@BruceForstall BruceForstall Mar 13, 2020

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nit: "store from"=>"stores from"

//
/*static*/ unsigned emitter::insGetLoadStoreRegisterListSize(instruction ins)
{
unsigned selem = 0;
unsigned registerListSize = 0;

switch (ins)
{
case INS_ld1:
case INS_ld1r:
case INS_st1:
selem = 1;
registerListSize = 1;
break;

case INS_ld1_2regs:
case INS_ld2:
case INS_ld2r:
case INS_st1_2regs:
case INS_st2:
selem = 2;
registerListSize = 2;
break;

case INS_ld1_3regs:
case INS_ld3:
case INS_ld3r:
case INS_st1_3regs:
case INS_st3:
selem = 3;
registerListSize = 3;
break;

case INS_ld1_4regs:
case INS_ld4:
case INS_ld4r:
case INS_st1_4regs:
case INS_st4:
selem = 4;
registerListSize = 4;
break;

default:
assert(!"Unexpected instruction");
break;
}

return selem;
return registerListSize;
}

// For the given 'arrangement' returns the 'datasize' specified by the vector register arrangement
Expand Down Expand Up @@ -4707,7 +4727,7 @@ void emitter::emitIns_R_R_I(
{
bool canEncode;
bitMaskImm bmi;
unsigned selem;
unsigned registerListSize;

case INS_mov:
// Check for the 'mov' aliases for the vector registers
Expand Down Expand Up @@ -5128,10 +5148,10 @@ void emitter::emitIns_R_R_I(

if (insOptsAnyArrangement(opt))
{
selem = insGetLoadStoreVectorSelem(ins);
registerListSize = insGetLoadStoreRegisterListSize(ins);
assert(isValidVectorDatasize(size));
assert(isValidArrangement(size, opt));
assert((size * selem) == imm);
assert((size * registerListSize) == imm);

// Load/Store multiple structures post-indexed by an immediate
fmt = IF_LS_2E;
Expand Down Expand Up @@ -5161,9 +5181,9 @@ void emitter::emitIns_R_R_I(
assert(isValidVectorDatasize(size));
assert(isValidArrangement(size, opt));

elemsize = optGetElemsize(opt);
selem = insGetLoadStoreVectorSelem(ins);
assert((elemsize * selem) == imm);
elemsize = optGetElemsize(opt);
registerListSize = insGetLoadStoreRegisterListSize(ins);
assert((elemsize * registerListSize) == imm);

// Load single structure and replicate post-indexed by an immediate
reg2 = encodingSPtoZR(reg2);
Expand Down Expand Up @@ -6298,7 +6318,7 @@ void emitter::emitIns_R_R_I_I(
int lsb;
int width;
bitMaskImm bmi;
unsigned selem;
unsigned registerListSize;

case INS_bfm:
case INS_sbfm:
Expand Down Expand Up @@ -6380,8 +6400,8 @@ void emitter::emitIns_R_R_I_I(
assert(isValidVectorElemsize(elemsize));
assert(isValidVectorIndex(EA_16BYTE, elemsize, imm1));

selem = insGetLoadStoreVectorSelem(ins);
assert((elemsize * selem) == (unsigned)imm2);
registerListSize = insGetLoadStoreRegisterListSize(ins);
assert((elemsize * registerListSize) == (unsigned)imm2);
assert(insOptsPostIndex(opt));

// Load/Store single structure post-indexed by an immediate
Expand Down Expand Up @@ -11431,7 +11451,7 @@ void emitter::emitDispIns(
emitAttr dstsize;
ssize_t index;
ssize_t index2;
unsigned selem;
unsigned registerListSize;

case IF_BI_0A: // BI_0A ......iiiiiiiiii iiiiiiiiiiiiiiii simm26:00
case IF_BI_0B: // BI_0B ......iiiiiiiiii iiiiiiiiiii..... simm19:00
Expand Down Expand Up @@ -11608,8 +11628,8 @@ void emitter::emitDispIns(

case IF_LS_2D: // LS_2D .Q.............. ....ssnnnnnttttt Vt Rn
case IF_LS_2E: // LS_2E .Q.............. ....ssnnnnnttttt Vt Rn
selem = insGetLoadStoreVectorSelem(id->idIns());
emitDispVectorRegList(id->idReg1(), selem, id->idInsOpt(), true);
registerListSize = insGetLoadStoreRegisterListSize(id->idIns());
emitDispVectorRegList(id->idReg1(), registerListSize, id->idInsOpt(), true);

if (fmt == IF_LS_2D)
{
Expand All @@ -11627,9 +11647,9 @@ void emitter::emitDispIns(

case IF_LS_2F: // LS_2F .Q.............. ...Sssnnnnnttttt Vt[] Rn
case IF_LS_2G: // LS_2G .Q.............. ...Sssnnnnnttttt Vt[] Rn
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@briansull briansull Mar 13, 2020 •
edited
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This should have the xx fields as well:

.Q.............. xx.Sssnnnnnttttt Vt[] Rn

selem = insGetLoadStoreVectorSelem(id->idIns());
elemsize = id->idOpSize();
emitDispVectorElemList(id->idReg1(), selem, elemsize, id->idSmallCns(), true);
registerListSize = insGetLoadStoreRegisterListSize(id->idIns());
elemsize = id->idOpSize();
emitDispVectorElemList(id->idReg1(), registerListSize, elemsize, id->idSmallCns(), true);

if (fmt == IF_LS_2F)
{
Expand All @@ -11639,7 +11659,7 @@ void emitter::emitDispIns(
else
{
// Load/Store single structure post-indexed by an immediate
emitDispAddrRI(id->idReg2(), INS_OPTS_POST_INDEX, (selem * elemsize));
emitDispAddrRI(id->idReg2(), INS_OPTS_POST_INDEX, (registerListSize * elemsize));
}
break;

Expand Down Expand Up @@ -11691,19 +11711,19 @@ void emitter::emitDispIns(

case IF_LS_3F: // LS_3F .Q.........mmmmm ....ssnnnnnttttt Vt Rn Rm
case IF_LS_3G: // LS_3G .Q.........mmmmm ...Sssnnnnnttttt Vt[] Rn Rm
selem = insGetLoadStoreVectorSelem(id->idIns());
registerListSize = insGetLoadStoreRegisterListSize(id->idIns());

if (fmt == IF_LS_3F)
{
// Load/Store multiple structures post-indexed by a register
// Load single structure and replicate post-indexed by a register
emitDispVectorRegList(id->idReg1(), selem, id->idInsOpt(), true);
emitDispVectorRegList(id->idReg1(), registerListSize, id->idInsOpt(), true);
}
else
{
// Load/Store single structure post-indexed by a register
elemsize = id->idOpSize();
emitDispVectorElemList(id->idReg1(), selem, elemsize, id->idSmallCns(), true);
emitDispVectorElemList(id->idReg1(), registerListSize, elemsize, id->idSmallCns(), true);
}

printf("[");
Expand Down
5 changes: 3 additions & 2 deletions src/coreclr/src/jit/emitarm64.h
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Original file line number Diff line number Diff line change
Expand Up @@ -448,8 +448,9 @@ static emitAttr optGetSrcsize(insOpts conversion);
// for an element of size 'elemsize' in a vector register of size 'datasize'
static bool isValidVectorIndex(emitAttr datasize, emitAttr elemsize, ssize_t index);

// For a given Load/Store Vector instruction 'ins' returns a number of structure elements
static unsigned insGetLoadStoreVectorSelem(instruction ins);
// For a given Load/Store Vector instruction 'ins' returns a number of consecutive SIMD registers
// the instruction loads to/store from.
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@BruceForstall BruceForstall Mar 13, 2020

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nit: "store from" => "stores from"

static unsigned insGetLoadStoreRegisterListSize(instruction ins);
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@BruceForstall BruceForstall Mar 13, 2020

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nit: ListSize => ListLength?


/************************************************************************/
/* Public inline informational methods */
Expand Down